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124ed0f6d8
Add FSP-I arch config PPI header file and GUID for supporting FSP-I to get Bootloader MM FV address and length, Bootloader MM FV context Data address and length under dispatch mode Signed-off-by: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Duggapu Chinni B <chinni.b.duggapu@intel.com> Cc: Ted Kuo <ted.kuo@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
55 lines
1.5 KiB
C
55 lines
1.5 KiB
C
/** @file
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Header file for FSP-I Arch Config PPI for Dispatch mode
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Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _FSPI_ARCH_CONFIG_PPI_H_
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#define _FSPI_ARCH_CONFIG_PPI_H_
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#define FSPI_ARCH_CONFIG_PPI_REVISION 0x1
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///
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/// Global ID for the FSPI_ARCH_CONFIG_PPI.
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///
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#define FSPI_ARCH_CONFIG_GUID \
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{ \
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0x15735ef9, 0x84ac, 0x4e34, { 0x98, 0x86, 0x56, 0xee, 0xcf, 0x73, 0xec, 0x0f } \
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}
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///
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/// This PPI provides FSP-I Arch Config PPI.
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///
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typedef struct {
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///
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/// Revision of the structure is 1 for this version of the specification.
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///
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UINT8 Revision;
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UINT8 Reserved[3];
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///
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/// Pointer to the bootloader SMM firmware volume (FV).
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///
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VOID *BootloaderSmmFvBaseAddress;
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///
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/// The length in bytes of the bootloader SMM firmware volume (FV).
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///
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UINTN BootloaderSmmFvLength;
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///
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/// Pointer to the bootloader SMM FV context data.
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/// This data is provided to bootloader SMM drivers through a HOB by the FSP MM Foundation.
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///
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VOID *BootloaderSmmFvContextData;
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///
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/// The length in bytes of the bootloader SMM FV context data.
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/// This data is provided to bootloader SMM drivers through a HOB by the FSP MM Foundation.
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///
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UINT16 BootloaderSmmFvContextDataLength;
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} FSPI_ARCH_CONFIG_PPI;
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extern EFI_GUID gFspiArchConfigPpiGuid;
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#endif // _FSPI_ARCH_CONFIG_PPI_H_
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