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d9715c133f
RNDR is a standard register defined in the ARM ARM for AARCH64. Move the definition from BaseRngLib to AArch64.h. Furthermore, move the inclusion of this register definition to the ARM specific header file. Signed-off-by: Oliver Smith-Denny <osde@microsoft.com>
255 lines
5.3 KiB
C
255 lines
5.3 KiB
C
/** @file
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef AARCH64_H_
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#define AARCH64_H_
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#include <AArch64/AArch64Mmu.h>
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// ARM Interrupt ID in Exception Table
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#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_AARCH64_IRQ
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// CPACR - Coprocessor Access Control Register definitions
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#define CPACR_TTA_EN (1UL << 28)
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#define CPACR_FPEN_EL1 (1UL << 20)
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#define CPACR_FPEN_FULL (3UL << 20)
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#define CPACR_DEFAULT CPACR_FPEN_FULL
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// Coprocessor Trap Register (CPTR)
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#define AARCH64_CPTR_TFP (1 << 10)
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#define AARCH64_CPTR_RES1 0x33ff
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#define AARCH64_CPTR_DEFAULT AARCH64_CPTR_RES1
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// ID_AA64MMFR1 - AArch64 Memory Model Feature Register 0 definitions
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#define AARCH64_MMFR1_VH (0xF << 8)
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// ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions
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#define AARCH64_PFR0_FP (0xF << 16)
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#define AARCH64_PFR0_GIC (0xF << 24)
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// ID_AA64DFR0 - AArch64 Debug Feature Register 0 definitions
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#define AARCH64_DFR0_TRACEVER (0xFULL << 4)
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#define AARCH64_DFR0_TRBE (0xFULL << 44)
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// SCR - Secure Configuration Register definitions
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#define SCR_NS (1 << 0)
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#define SCR_IRQ (1 << 1)
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#define SCR_FIQ (1 << 2)
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#define SCR_EA (1 << 3)
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#define SCR_FW (1 << 4)
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#define SCR_AW (1 << 5)
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// MIDR - Main ID Register definitions
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#define ARM_CPU_TYPE_SHIFT 4
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#define ARM_CPU_TYPE_MASK 0xFFF
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#define ARM_CPU_TYPE_AEMV8 0xD0F
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#define ARM_CPU_TYPE_A53 0xD03
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#define ARM_CPU_TYPE_A57 0xD07
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#define ARM_CPU_TYPE_A72 0xD08
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#define ARM_CPU_TYPE_A15 0xC0F
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#define ARM_CPU_TYPE_A9 0xC09
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#define ARM_CPU_TYPE_A7 0xC07
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#define ARM_CPU_TYPE_A5 0xC05
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#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )
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#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))
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// Hypervisor Configuration Register
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#define ARM_HCR_FMO BIT3
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#define ARM_HCR_IMO BIT4
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#define ARM_HCR_AMO BIT5
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#define ARM_HCR_TSC BIT19
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#define ARM_HCR_TGE BIT27
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#define ARM_HCR_E2H BIT34
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// Exception Syndrome Register
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#define AARCH64_ESR_EC(Ecr) ((0x3F << 26) & (Ecr))
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#define AARCH64_ESR_ISS(Ecr) ((0x1FFFFFF) & (Ecr))
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#define AARCH64_ESR_EC_SMC32 (0x13 << 26)
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#define AARCH64_ESR_EC_SMC64 (0x17 << 26)
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// AArch64 Exception Level
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#define AARCH64_EL3 0xC
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#define AARCH64_EL2 0x8
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#define AARCH64_EL1 0x4
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// Saved Program Status Register definitions
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#define SPSR_A BIT8
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#define SPSR_I BIT7
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#define SPSR_F BIT6
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#define SPSR_AARCH32 BIT4
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#define SPSR_AARCH32_MODE_USER 0x0
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#define SPSR_AARCH32_MODE_FIQ 0x1
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#define SPSR_AARCH32_MODE_IRQ 0x2
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#define SPSR_AARCH32_MODE_SVC 0x3
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#define SPSR_AARCH32_MODE_ABORT 0x7
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#define SPSR_AARCH32_MODE_UNDEF 0xB
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#define SPSR_AARCH32_MODE_SYS 0xF
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// Counter-timer Hypervisor Control register definitions
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#define CNTHCTL_EL2_EL1PCTEN BIT0
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#define CNTHCTL_EL2_EL1PCEN BIT1
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#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1)
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// Vector table offset definitions
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#define ARM_VECTOR_CUR_SP0_SYNC 0x000
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#define ARM_VECTOR_CUR_SP0_IRQ 0x080
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#define ARM_VECTOR_CUR_SP0_FIQ 0x100
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#define ARM_VECTOR_CUR_SP0_SERR 0x180
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#define ARM_VECTOR_CUR_SPX_SYNC 0x200
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#define ARM_VECTOR_CUR_SPX_IRQ 0x280
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#define ARM_VECTOR_CUR_SPX_FIQ 0x300
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#define ARM_VECTOR_CUR_SPX_SERR 0x380
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#define ARM_VECTOR_LOW_A64_SYNC 0x400
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#define ARM_VECTOR_LOW_A64_IRQ 0x480
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#define ARM_VECTOR_LOW_A64_FIQ 0x500
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#define ARM_VECTOR_LOW_A64_SERR 0x580
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#define ARM_VECTOR_LOW_A32_SYNC 0x600
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#define ARM_VECTOR_LOW_A32_IRQ 0x680
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#define ARM_VECTOR_LOW_A32_FIQ 0x700
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#define ARM_VECTOR_LOW_A32_SERR 0x780
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// The ID_AA64ISAR2_EL1 register is not recognized by older
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// assemblers, we need to define it here.
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#define ID_AA64ISAR2_EL1 S3_0_C0_C6_2
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// The ID_AA64MMFR2_EL1 register was added in ARMv8.2. Since we
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// build for ARMv8.0, we need to define the register here.
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#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
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// The RNDR register is not recognized by older assemblers,
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// so we need to define it here
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#define RNDR S3_3_C2_C4_0
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#define VECTOR_BASE(tbl) \
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.section .text.##tbl##,"ax"; \
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.align 11; \
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.org 0x0; \
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GCC_ASM_EXPORT(tbl); \
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ASM_PFX(tbl): \
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#define VECTOR_ENTRY(tbl, off) \
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.org off
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#define VECTOR_END(tbl) \
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.org 0x800; \
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.previous
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VOID
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EFIAPI
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ArmEnableSWPInstruction (
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VOID
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);
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UINTN
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EFIAPI
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ArmReadCbar (
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VOID
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);
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UINTN
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EFIAPI
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ArmReadTpidrurw (
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VOID
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);
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VOID
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EFIAPI
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ArmWriteTpidrurw (
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UINTN Value
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);
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UINTN
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EFIAPI
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ArmGetTCR (
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VOID
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);
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VOID
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EFIAPI
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ArmSetTCR (
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UINTN Value
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);
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UINTN
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EFIAPI
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ArmGetMAIR (
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VOID
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);
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VOID
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EFIAPI
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ArmSetMAIR (
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UINTN Value
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);
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VOID
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EFIAPI
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ArmDisableAlignmentCheck (
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VOID
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);
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VOID
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EFIAPI
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ArmEnableAlignmentCheck (
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VOID
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);
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VOID
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EFIAPI
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ArmDisableStackAlignmentCheck (
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VOID
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);
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VOID
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EFIAPI
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ArmEnableStackAlignmentCheck (
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VOID
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);
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VOID
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EFIAPI
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ArmDisableAllExceptions (
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VOID
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);
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VOID
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ArmWriteHcr (
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IN UINTN Hcr
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);
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UINTN
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ArmReadHcr (
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VOID
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);
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UINTN
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ArmReadCurrentEL (
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VOID
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);
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UINT32
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ArmReadCntHctl (
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VOID
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);
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VOID
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ArmWriteCntHctl (
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IN UINT32 CntHctl
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);
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#endif // AARCH64_H_
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