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c4c7fb2174
Add the BTI instructions and the associated note to make the AArch64 asm objects compatible with BTI enforcement. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
33 lines
920 B
ArmAsm
33 lines
920 B
ArmAsm
#------------------------------------------------------------------------------
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#
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# CpuBreakpoint() for AArch64
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#
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# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
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# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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#------------------------------------------------------------------------------
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.text
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.p2align 2
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GCC_ASM_EXPORT(CpuBreakpoint)
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#/**
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# Generates a breakpoint on the CPU.
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#
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# Generates a breakpoint on the CPU. The breakpoint must be implemented such
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# that code can resume normal execution after the breakpoint.
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#
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#**/
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#VOID
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#EFIAPI
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#CpuBreakpoint (
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# VOID
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# );
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#
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ASM_PFX(CpuBreakpoint):
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AARCH64_BTI(c)
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svc 0xdbdb // Superviser exception. Takes 16bit arg -> Armv7 had 'swi' here.
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ret
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