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c4c7fb2174
Add the BTI instructions and the associated note to make the AArch64 asm objects compatible with BTI enforcement. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
41 lines
1.1 KiB
ArmAsm
41 lines
1.1 KiB
ArmAsm
#------------------------------------------------------------------------------
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#
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# GetInterruptState() function for AArch64
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#
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# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
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# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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#------------------------------------------------------------------------------
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.text
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.p2align 2
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GCC_ASM_EXPORT(GetInterruptState)
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.set DAIF_RD_IRQ_BIT, (1 << 7)
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#/**
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# Retrieves the current CPU interrupt state.
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#
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# Returns TRUE is interrupts are currently enabled. Otherwise
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# returns FALSE.
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#
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# @retval TRUE CPU interrupts are enabled.
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# @retval FALSE CPU interrupts are disabled.
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#
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#**/
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#
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#BOOLEAN
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#EFIAPI
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#GetInterruptState (
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# VOID
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# );
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#
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ASM_PFX(GetInterruptState):
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AARCH64_BTI(c)
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mrs x0, daif
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tst x0, #DAIF_RD_IRQ_BIT // Check IRQ mask; set Z=1 if clear/unmasked
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cset w0, eq // if Z=1 (eq) return 1, else 0
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ret
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