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57684402e4
Adding SetExceptionBaseAddress and SetTlbRebaseAddress functions for LoongArch64. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
42 lines
1.2 KiB
ArmAsm
42 lines
1.2 KiB
ArmAsm
#------------------------------------------------------------------------------
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#
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# LoongArch set exception base address operations
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#
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# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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#------------------------------------------------------------------------------
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#include <Base.h>
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#include <Register/LoongArch64/Csr.h>
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ASM_GLOBAL ASM_PFX(SetExceptionBaseAddress)
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ASM_GLOBAL ASM_PFX(SetTlbRebaseAddress)
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#/**
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# Set the exception base address for LoongArch.
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#
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# @param ExceptionBaseAddress The exception base address, must be aligned greater than or qeual to 4K .
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#**/
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ASM_PFX(SetExceptionBaseAddress):
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csrrd $t0, LOONGARCH_CSR_ECFG
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li.d $t1, ~(BIT16 | BIT17 | BIT18)
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and $t0, $t0, $t1
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csrwr $t0, LOONGARCH_CSR_ECFG
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move $t0, $a0
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csrwr $t0, LOONGARCH_CSR_EBASE
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jirl $zero, $ra, 0
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#/**
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# Set the TlbRebase address for LoongArch.
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#
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# @param TlbRebaseAddress The TlbRebase address, must be aligned greater than or qeual to 4K .
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#**/
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ASM_PFX(SetTlbRebaseAddress):
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move $t0, $a0
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csrwr $t0, LOONGARCH_CSR_TLBREBASE
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jirl $zero, $ra, 0
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.end
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