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b54bc983c6
The ratified RISC-V crypto scalar extensions provide entropy bits via the seed CSR, as exposed by the Zkr extension. The Zkr extension is ratified and provides 16 bits of entropy seed when reading the SEED CSR. Guarded by a RISCV64 Feature PCD, 64-bit random numbers can be accumulated from the `seed` CSR. This driver is based on the driver in the Linux kernel. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Co-authored-by: Tim Wawrzynczak <tim@rivosinc.com>
20 lines
501 B
ArmAsm
20 lines
501 B
ArmAsm
//------------------------------------------------------------------------------
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//
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// RISC-V cache operation.
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//
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// Copyright (c) 2024, Rivos Inc. All rights reserved.<BR>
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//
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// SPDX-License-Identifier: BSD-2-Clause-Patent
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//
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//------------------------------------------------------------------------------
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#include <Register/RiscV64/RiscVImpl.h>
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.text
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.p2align 4
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ASM_FUNC (ReadSeed)
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#The SEED CSR must only be accessed with read-write instructions
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csrrw a0, CSR_SEED, x0
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ret
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