mirror of https://github.com/acidanthera/audk.git
1374 lines
48 KiB
C
1374 lines
48 KiB
C
/** @file
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Provide common routines used by BasePciSegmentLibSegmentInfo and
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DxeRuntimePciSegmentLibSegmentInfo libraries.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PciSegmentLibCommon.h"
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typedef struct {
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UINT32 Register : 12;
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UINT32 Function : 3;
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UINT32 Device : 5;
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UINT32 Bus : 8;
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UINT32 Reserved1 : 4;
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UINT32 Segment : 16;
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UINT32 Reserved2 : 16;
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} PCI_SEGMENT_LIB_ADDRESS_STRUCTURE;
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/**
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Internal function that converts PciSegmentLib format address that encodes the PCI Bus, Device,
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Function and Register to ECAM (Enhanced Configuration Access Mechanism) address.
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@param Address The address that encodes the PCI Bus, Device, Function and
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Register.
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@param SegmentInfo An array of PCI_SEGMENT_INFO holding the segment information.
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@param Count Number of segments.
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@retval ECAM address.
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**/
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UINTN
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PciSegmentLibGetEcamAddress (
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IN UINT64 Address,
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IN CONST PCI_SEGMENT_INFO *SegmentInfo,
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IN UINTN Count
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)
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{
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while (Count != 0) {
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if (SegmentInfo->SegmentNumber == ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Segment) {
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break;
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}
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SegmentInfo++;
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Count--;
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}
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ASSERT (Count != 0);
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ASSERT (
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(((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Reserved1 == 0) &&
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(((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Reserved2 == 0)
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);
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ASSERT (((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Bus >= SegmentInfo->StartBusNumber);
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ASSERT (((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Bus <= SegmentInfo->EndBusNumber);
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Address = SegmentInfo->BaseAddress + PCI_ECAM_ADDRESS (
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((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Bus,
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((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Device,
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((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Function,
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((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Register
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);
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if (sizeof (UINTN) == sizeof (UINT32)) {
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ASSERT (Address < BASE_4GB);
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}
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return PciSegmentLibVirtualAddress ((UINTN)Address);
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}
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/**
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Reads an 8-bit PCI configuration register.
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Reads and returns the 8-bit PCI configuration register specified by Address.
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This function must guarantee that all PCI read and write operations are serialized.
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If any reserved bits in Address are set, then ASSERT().
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@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
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@return The 8-bit PCI configuration register specified by Address.
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**/
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UINT8
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EFIAPI
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PciSegmentRead8 (
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IN UINT64 Address
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)
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{
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UINTN Count;
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PCI_SEGMENT_INFO *SegmentInfo;
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SegmentInfo = GetPciSegmentInfo (&Count);
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return MmioRead8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count));
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}
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/**
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Writes an 8-bit PCI configuration register.
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Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
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Value is returned. This function must guarantee that all PCI read and write operations are serialized.
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If any reserved bits in Address are set, then ASSERT().
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@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
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@param Value The value to write.
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@return The value written to the PCI configuration register.
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**/
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UINT8
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EFIAPI
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PciSegmentWrite8 (
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IN UINT64 Address,
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IN UINT8 Value
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)
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{
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UINTN Count;
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PCI_SEGMENT_INFO *SegmentInfo;
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SegmentInfo = GetPciSegmentInfo (&Count);
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return MmioWrite8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), Value);
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}
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/**
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Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.
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Reads the 8-bit PCI configuration register specified by Address,
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performs a bitwise OR between the read result and the value specified by OrData,
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and writes the result to the 8-bit PCI configuration register specified by Address.
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The value written to the PCI configuration register is returned.
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This function must guarantee that all PCI read and write operations are serialized.
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If any reserved bits in Address are set, then ASSERT().
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@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
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@param OrData The value to OR with the PCI configuration register.
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@return The value written to the PCI configuration register.
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**/
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UINT8
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EFIAPI
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PciSegmentOr8 (
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IN UINT64 Address,
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IN UINT8 OrData
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)
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{
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UINTN Count;
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PCI_SEGMENT_INFO *SegmentInfo;
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SegmentInfo = GetPciSegmentInfo (&Count);
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return MmioOr8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), OrData);
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}
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/**
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Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
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Reads the 8-bit PCI configuration register specified by Address,
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performs a bitwise AND between the read result and the value specified by AndData,
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and writes the result to the 8-bit PCI configuration register specified by Address.
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The value written to the PCI configuration register is returned.
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This function must guarantee that all PCI read and write operations are serialized.
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If any reserved bits in Address are set, then ASSERT().
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@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
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@param AndData The value to AND with the PCI configuration register.
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@return The value written to the PCI configuration register.
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**/
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UINT8
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EFIAPI
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PciSegmentAnd8 (
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IN UINT64 Address,
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IN UINT8 AndData
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)
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{
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UINTN Count;
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PCI_SEGMENT_INFO *SegmentInfo;
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SegmentInfo = GetPciSegmentInfo (&Count);
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return MmioAnd8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData);
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}
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/**
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Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
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followed a bitwise OR with another 8-bit value.
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Reads the 8-bit PCI configuration register specified by Address,
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performs a bitwise AND between the read result and the value specified by AndData,
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performs a bitwise OR between the result of the AND operation and the value specified by OrData,
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and writes the result to the 8-bit PCI configuration register specified by Address.
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The value written to the PCI configuration register is returned.
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This function must guarantee that all PCI read and write operations are serialized.
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If any reserved bits in Address are set, then ASSERT().
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@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
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@param AndData The value to AND with the PCI configuration register.
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@param OrData The value to OR with the PCI configuration register.
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@return The value written to the PCI configuration register.
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**/
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UINT8
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EFIAPI
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PciSegmentAndThenOr8 (
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IN UINT64 Address,
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IN UINT8 AndData,
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IN UINT8 OrData
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)
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{
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UINTN Count;
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PCI_SEGMENT_INFO *SegmentInfo;
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SegmentInfo = GetPciSegmentInfo (&Count);
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return MmioAndThenOr8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData, OrData);
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}
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/**
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Reads a bit field of a PCI configuration register.
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Reads the bit field in an 8-bit PCI configuration register. The bit field is
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specified by the StartBit and the EndBit. The value of the bit field is
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returned.
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If any reserved bits in Address are set, then ASSERT().
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If StartBit is greater than 7, then ASSERT().
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If EndBit is greater than 7, then ASSERT().
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If EndBit is less than StartBit, then ASSERT().
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@param Address PCI configuration register to read.
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@param StartBit The ordinal of the least significant bit in the bit field.
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Range 0..7.
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@param EndBit The ordinal of the most significant bit in the bit field.
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Range 0..7.
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@return The value of the bit field read from the PCI configuration register.
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**/
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UINT8
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EFIAPI
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PciSegmentBitFieldRead8 (
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IN UINT64 Address,
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IN UINTN StartBit,
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IN UINTN EndBit
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)
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{
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UINTN Count;
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PCI_SEGMENT_INFO *SegmentInfo;
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SegmentInfo = GetPciSegmentInfo (&Count);
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return MmioBitFieldRead8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit);
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}
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/**
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Writes a bit field to a PCI configuration register.
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Writes Value to the bit field of the PCI configuration register. The bit
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field is specified by the StartBit and the EndBit. All other bits in the
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destination PCI configuration register are preserved. The new value of the
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8-bit register is returned.
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If any reserved bits in Address are set, then ASSERT().
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If StartBit is greater than 7, then ASSERT().
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If EndBit is greater than 7, then ASSERT().
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If EndBit is less than StartBit, then ASSERT().
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If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
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@param Address PCI configuration register to write.
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@param StartBit The ordinal of the least significant bit in the bit field.
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Range 0..7.
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@param EndBit The ordinal of the most significant bit in the bit field.
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Range 0..7.
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@param Value New value of the bit field.
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@return The value written back to the PCI configuration register.
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**/
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UINT8
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EFIAPI
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PciSegmentBitFieldWrite8 (
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IN UINT64 Address,
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IN UINTN StartBit,
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IN UINTN EndBit,
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IN UINT8 Value
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)
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{
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UINTN Count;
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PCI_SEGMENT_INFO *SegmentInfo;
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SegmentInfo = GetPciSegmentInfo (&Count);
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return MmioBitFieldWrite8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, Value);
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}
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/**
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Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
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writes the result back to the bit field in the 8-bit port.
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Reads the 8-bit PCI configuration register specified by Address, performs a
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bitwise OR between the read result and the value specified by
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OrData, and writes the result to the 8-bit PCI configuration register
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specified by Address. The value written to the PCI configuration register is
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returned. This function must guarantee that all PCI read and write operations
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are serialized. Extra left bits in OrData are stripped.
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If any reserved bits in Address are set, then ASSERT().
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If StartBit is greater than 7, then ASSERT().
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If EndBit is greater than 7, then ASSERT().
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If EndBit is less than StartBit, then ASSERT().
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If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
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@param Address PCI configuration register to write.
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@param StartBit The ordinal of the least significant bit in the bit field.
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Range 0..7.
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@param EndBit The ordinal of the most significant bit in the bit field.
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Range 0..7.
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@param OrData The value to OR with the PCI configuration register.
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@return The value written back to the PCI configuration register.
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**/
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UINT8
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EFIAPI
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PciSegmentBitFieldOr8 (
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IN UINT64 Address,
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IN UINTN StartBit,
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IN UINTN EndBit,
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IN UINT8 OrData
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)
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{
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UINTN Count;
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PCI_SEGMENT_INFO *SegmentInfo;
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SegmentInfo = GetPciSegmentInfo (&Count);
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return MmioBitFieldOr8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, OrData);
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}
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/**
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Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
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AND, and writes the result back to the bit field in the 8-bit register.
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Reads the 8-bit PCI configuration register specified by Address, performs a
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bitwise AND between the read result and the value specified by AndData, and
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writes the result to the 8-bit PCI configuration register specified by
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Address. The value written to the PCI configuration register is returned.
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This function must guarantee that all PCI read and write operations are
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serialized. Extra left bits in AndData are stripped.
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If any reserved bits in Address are set, then ASSERT().
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If StartBit is greater than 7, then ASSERT().
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If EndBit is greater than 7, then ASSERT().
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If EndBit is less than StartBit, then ASSERT().
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If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
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@param Address PCI configuration register to write.
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@param StartBit The ordinal of the least significant bit in the bit field.
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Range 0..7.
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@param EndBit The ordinal of the most significant bit in the bit field.
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Range 0..7.
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@param AndData The value to AND with the PCI configuration register.
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@return The value written back to the PCI configuration register.
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**/
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UINT8
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EFIAPI
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PciSegmentBitFieldAnd8 (
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IN UINT64 Address,
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IN UINTN StartBit,
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IN UINTN EndBit,
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IN UINT8 AndData
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)
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{
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UINTN Count;
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PCI_SEGMENT_INFO *SegmentInfo;
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SegmentInfo = GetPciSegmentInfo (&Count);
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return MmioBitFieldAnd8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData);
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}
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/**
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Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
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bitwise OR, and writes the result back to the bit field in the 8-bit port.
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Reads the 8-bit PCI configuration register specified by Address, performs a
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bitwise AND followed by a bitwise OR between the read result and
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the value specified by AndData, and writes the result to the 8-bit PCI
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configuration register specified by Address. The value written to the PCI
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configuration register is returned. This function must guarantee that all PCI
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read and write operations are serialized. Extra left bits in both AndData and
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OrData are stripped.
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If any reserved bits in Address are set, then ASSERT().
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If StartBit is greater than 7, then ASSERT().
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If EndBit is greater than 7, then ASSERT().
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If EndBit is less than StartBit, then ASSERT().
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If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
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If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
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@param Address PCI configuration register to write.
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@param StartBit The ordinal of the least significant bit in the bit field.
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Range 0..7.
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@param EndBit The ordinal of the most significant bit in the bit field.
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Range 0..7.
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@param AndData The value to AND with the PCI configuration register.
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@param OrData The value to OR with the result of the AND operation.
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@return The value written back to the PCI configuration register.
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**/
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UINT8
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EFIAPI
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PciSegmentBitFieldAndThenOr8 (
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IN UINT64 Address,
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IN UINTN StartBit,
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IN UINTN EndBit,
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IN UINT8 AndData,
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IN UINT8 OrData
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)
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{
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UINTN Count;
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PCI_SEGMENT_INFO *SegmentInfo;
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SegmentInfo = GetPciSegmentInfo (&Count);
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return MmioBitFieldAndThenOr8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData, OrData);
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}
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/**
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Reads a 16-bit PCI configuration register.
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Reads and returns the 16-bit PCI configuration register specified by Address.
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This function must guarantee that all PCI read and write operations are serialized.
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|
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If any reserved bits in Address are set, then ASSERT().
|
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If Address is not aligned on a 16-bit boundary, then ASSERT().
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|
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@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
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@return The 16-bit PCI configuration register specified by Address.
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**/
|
|
UINT16
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EFIAPI
|
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PciSegmentRead16 (
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IN UINT64 Address
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)
|
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{
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UINTN Count;
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PCI_SEGMENT_INFO *SegmentInfo;
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SegmentInfo = GetPciSegmentInfo (&Count);
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return MmioRead16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count));
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}
|
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|
|
/**
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Writes a 16-bit PCI configuration register.
|
|
|
|
Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
|
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Value is returned. This function must guarantee that all PCI read and write operations are serialized.
|
|
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If any reserved bits in Address are set, then ASSERT().
|
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
|
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@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
|
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@param Value The value to write.
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@return The parameter of Value.
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**/
|
|
UINT16
|
|
EFIAPI
|
|
PciSegmentWrite16 (
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IN UINT64 Address,
|
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IN UINT16 Value
|
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)
|
|
{
|
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UINTN Count;
|
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PCI_SEGMENT_INFO *SegmentInfo;
|
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|
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SegmentInfo = GetPciSegmentInfo (&Count);
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return MmioWrite16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), Value);
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}
|
|
|
|
/**
|
|
Performs a bitwise OR of a 16-bit PCI configuration register with
|
|
a 16-bit value.
|
|
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|
Reads the 16-bit PCI configuration register specified by Address, performs a
|
|
bitwise OR between the read result and the value specified by OrData, and
|
|
writes the result to the 16-bit PCI configuration register specified by Address.
|
|
The value written to the PCI configuration register is returned. This function
|
|
must guarantee that all PCI read and write operations are serialized.
|
|
|
|
If any reserved bits in Address are set, then ASSERT().
|
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
|
|
@param Address Address that encodes the PCI Segment, Bus, Device, Function and
|
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Register.
|
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@param OrData The value to OR with the PCI configuration register.
|
|
|
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@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT16
|
|
EFIAPI
|
|
PciSegmentOr16 (
|
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IN UINT64 Address,
|
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IN UINT16 OrData
|
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)
|
|
{
|
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UINTN Count;
|
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PCI_SEGMENT_INFO *SegmentInfo;
|
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|
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SegmentInfo = GetPciSegmentInfo (&Count);
|
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return MmioOr16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), OrData);
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|
}
|
|
|
|
/**
|
|
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
|
|
|
|
Reads the 16-bit PCI configuration register specified by Address,
|
|
performs a bitwise AND between the read result and the value specified by AndData,
|
|
and writes the result to the 16-bit PCI configuration register specified by Address.
|
|
The value written to the PCI configuration register is returned.
|
|
This function must guarantee that all PCI read and write operations are serialized.
|
|
|
|
If any reserved bits in Address are set, then ASSERT().
|
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
|
|
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
|
|
@param AndData The value to AND with the PCI configuration register.
|
|
|
|
@return The value written to the PCI configuration register.
|
|
|
|
**/
|
|
UINT16
|
|
EFIAPI
|
|
PciSegmentAnd16 (
|
|
IN UINT64 Address,
|
|
IN UINT16 AndData
|
|
)
|
|
{
|
|
UINTN Count;
|
|
PCI_SEGMENT_INFO *SegmentInfo;
|
|
|
|
SegmentInfo = GetPciSegmentInfo (&Count);
|
|
return MmioAnd16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData);
|
|
}
|
|
|
|
/**
|
|
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
|
|
followed a bitwise OR with another 16-bit value.
|
|
|
|
Reads the 16-bit PCI configuration register specified by Address,
|
|
performs a bitwise AND between the read result and the value specified by AndData,
|
|
performs a bitwise OR between the result of the AND operation and the value specified by OrData,
|
|
and writes the result to the 16-bit PCI configuration register specified by Address.
|
|
The value written to the PCI configuration register is returned.
|
|
This function must guarantee that all PCI read and write operations are serialized.
|
|
|
|
If any reserved bits in Address are set, then ASSERT().
|
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
|
|
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
|
|
@param AndData The value to AND with the PCI configuration register.
|
|
@param OrData The value to OR with the PCI configuration register.
|
|
|
|
@return The value written to the PCI configuration register.
|
|
|
|
**/
|
|
UINT16
|
|
EFIAPI
|
|
PciSegmentAndThenOr16 (
|
|
IN UINT64 Address,
|
|
IN UINT16 AndData,
|
|
IN UINT16 OrData
|
|
)
|
|
{
|
|
UINTN Count;
|
|
PCI_SEGMENT_INFO *SegmentInfo;
|
|
|
|
SegmentInfo = GetPciSegmentInfo (&Count);
|
|
return MmioAndThenOr16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData, OrData);
|
|
}
|
|
|
|
/**
|
|
Reads a bit field of a PCI configuration register.
|
|
|
|
Reads the bit field in a 16-bit PCI configuration register. The bit field is
|
|
specified by the StartBit and the EndBit. The value of the bit field is
|
|
returned.
|
|
|
|
If any reserved bits in Address are set, then ASSERT().
|
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
If StartBit is greater than 15, then ASSERT().
|
|
If EndBit is greater than 15, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
|
|
@param Address PCI configuration register to read.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..15.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..15.
|
|
|
|
@return The value of the bit field read from the PCI configuration register.
|
|
|
|
**/
|
|
UINT16
|
|
EFIAPI
|
|
PciSegmentBitFieldRead16 (
|
|
IN UINT64 Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit
|
|
)
|
|
{
|
|
UINTN Count;
|
|
PCI_SEGMENT_INFO *SegmentInfo;
|
|
|
|
SegmentInfo = GetPciSegmentInfo (&Count);
|
|
return MmioBitFieldRead16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit);
|
|
}
|
|
|
|
/**
|
|
Writes a bit field to a PCI configuration register.
|
|
|
|
Writes Value to the bit field of the PCI configuration register. The bit
|
|
field is specified by the StartBit and the EndBit. All other bits in the
|
|
destination PCI configuration register are preserved. The new value of the
|
|
16-bit register is returned.
|
|
|
|
If any reserved bits in Address are set, then ASSERT().
|
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
If StartBit is greater than 15, then ASSERT().
|
|
If EndBit is greater than 15, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
|
@param Address PCI configuration register to write.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..15.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..15.
|
|
@param Value New value of the bit field.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT16
|
|
EFIAPI
|
|
PciSegmentBitFieldWrite16 (
|
|
IN UINT64 Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit,
|
|
IN UINT16 Value
|
|
)
|
|
{
|
|
UINTN Count;
|
|
PCI_SEGMENT_INFO *SegmentInfo;
|
|
|
|
SegmentInfo = GetPciSegmentInfo (&Count);
|
|
return MmioBitFieldWrite16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, Value);
|
|
}
|
|
|
|
/**
|
|
Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes
|
|
the result back to the bit field in the 16-bit port.
|
|
|
|
Reads the 16-bit PCI configuration register specified by Address, performs a
|
|
bitwise OR between the read result and the value specified by
|
|
OrData, and writes the result to the 16-bit PCI configuration register
|
|
specified by Address. The value written to the PCI configuration register is
|
|
returned. This function must guarantee that all PCI read and write operations
|
|
are serialized. Extra left bits in OrData are stripped.
|
|
|
|
If any reserved bits in Address are set, then ASSERT().
|
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
If StartBit is greater than 15, then ASSERT().
|
|
If EndBit is greater than 15, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
|
@param Address PCI configuration register to write.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..15.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..15.
|
|
@param OrData The value to OR with the PCI configuration register.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT16
|
|
EFIAPI
|
|
PciSegmentBitFieldOr16 (
|
|
IN UINT64 Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit,
|
|
IN UINT16 OrData
|
|
)
|
|
{
|
|
UINTN Count;
|
|
PCI_SEGMENT_INFO *SegmentInfo;
|
|
|
|
SegmentInfo = GetPciSegmentInfo (&Count);
|
|
return MmioBitFieldOr16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, OrData);
|
|
}
|
|
|
|
/**
|
|
Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
|
|
AND, writes the result back to the bit field in the 16-bit register.
|
|
|
|
Reads the 16-bit PCI configuration register specified by Address, performs a
|
|
bitwise AND between the read result and the value specified by AndData, and
|
|
writes the result to the 16-bit PCI configuration register specified by
|
|
Address. The value written to the PCI configuration register is returned.
|
|
This function must guarantee that all PCI read and write operations are
|
|
serialized. Extra left bits in AndData are stripped.
|
|
|
|
If any reserved bits in Address are set, then ASSERT().
|
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
If StartBit is greater than 15, then ASSERT().
|
|
If EndBit is greater than 15, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
|
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..15.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..15.
|
|
@param AndData The value to AND with the PCI configuration register.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT16
|
|
EFIAPI
|
|
PciSegmentBitFieldAnd16 (
|
|
IN UINT64 Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit,
|
|
IN UINT16 AndData
|
|
)
|
|
{
|
|
UINTN Count;
|
|
PCI_SEGMENT_INFO *SegmentInfo;
|
|
|
|
SegmentInfo = GetPciSegmentInfo (&Count);
|
|
return MmioBitFieldAnd16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData);
|
|
}
|
|
|
|
/**
|
|
Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
|
|
bitwise OR, and writes the result back to the bit field in the
|
|
16-bit port.
|
|
|
|
Reads the 16-bit PCI configuration register specified by Address, performs a
|
|
bitwise AND followed by a bitwise OR between the read result and
|
|
the value specified by AndData, and writes the result to the 16-bit PCI
|
|
configuration register specified by Address. The value written to the PCI
|
|
configuration register is returned. This function must guarantee that all PCI
|
|
read and write operations are serialized. Extra left bits in both AndData and
|
|
OrData are stripped.
|
|
|
|
If any reserved bits in Address are set, then ASSERT().
|
|
If StartBit is greater than 15, then ASSERT().
|
|
If EndBit is greater than 15, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
|
@param Address PCI configuration register to write.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..15.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..15.
|
|
@param AndData The value to AND with the PCI configuration register.
|
|
@param OrData The value to OR with the result of the AND operation.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT16
|
|
EFIAPI
|
|
PciSegmentBitFieldAndThenOr16 (
|
|
IN UINT64 Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit,
|
|
IN UINT16 AndData,
|
|
IN UINT16 OrData
|
|
)
|
|
{
|
|
UINTN Count;
|
|
PCI_SEGMENT_INFO *SegmentInfo;
|
|
|
|
SegmentInfo = GetPciSegmentInfo (&Count);
|
|
return MmioBitFieldAndThenOr16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData, OrData);
|
|
}
|
|
|
|
/**
|
|
Reads a 32-bit PCI configuration register.
|
|
|
|
Reads and returns the 32-bit PCI configuration register specified by Address.
|
|
This function must guarantee that all PCI read and write operations are serialized.
|
|
|
|
If any reserved bits in Address are set, then ASSERT().
|
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
|
|
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
|
|
|
|
@return The 32-bit PCI configuration register specified by Address.
|
|
|
|
**/
|
|
UINT32
|
|
EFIAPI
|
|
PciSegmentRead32 (
|
|
IN UINT64 Address
|
|
)
|
|
{
|
|
UINTN Count;
|
|
PCI_SEGMENT_INFO *SegmentInfo;
|
|
|
|
SegmentInfo = GetPciSegmentInfo (&Count);
|
|
return MmioRead32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count));
|
|
}
|
|
|
|
/**
|
|
Writes a 32-bit PCI configuration register.
|
|
|
|
Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
|
|
Value is returned. This function must guarantee that all PCI read and write operations are serialized.
|
|
|
|
If any reserved bits in Address are set, then ASSERT().
|
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
|
|
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
|
|
@param Value The value to write.
|
|
|
|
@return The parameter of Value.
|
|
|
|
**/
|
|
UINT32
|
|
EFIAPI
|
|
PciSegmentWrite32 (
|
|
IN UINT64 Address,
|
|
IN UINT32 Value
|
|
)
|
|
{
|
|
UINTN Count;
|
|
PCI_SEGMENT_INFO *SegmentInfo;
|
|
|
|
SegmentInfo = GetPciSegmentInfo (&Count);
|
|
return MmioWrite32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), Value);
|
|
}
|
|
|
|
/**
|
|
Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.
|
|
|
|
Reads the 32-bit PCI configuration register specified by Address,
|
|
performs a bitwise OR between the read result and the value specified by OrData,
|
|
and writes the result to the 32-bit PCI configuration register specified by Address.
|
|
The value written to the PCI configuration register is returned.
|
|
This function must guarantee that all PCI read and write operations are serialized.
|
|
|
|
If any reserved bits in Address are set, then ASSERT().
|
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
|
|
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
|
|
@param OrData The value to OR with the PCI configuration register.
|
|
|
|
@return The value written to the PCI configuration register.
|
|
|
|
**/
|
|
UINT32
|
|
EFIAPI
|
|
PciSegmentOr32 (
|
|
IN UINT64 Address,
|
|
IN UINT32 OrData
|
|
)
|
|
{
|
|
UINTN Count;
|
|
PCI_SEGMENT_INFO *SegmentInfo;
|
|
|
|
SegmentInfo = GetPciSegmentInfo (&Count);
|
|
return MmioOr32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), OrData);
|
|
}
|
|
|
|
/**
|
|
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
|
|
|
|
Reads the 32-bit PCI configuration register specified by Address,
|
|
performs a bitwise AND between the read result and the value specified by AndData,
|
|
and writes the result to the 32-bit PCI configuration register specified by Address.
|
|
The value written to the PCI configuration register is returned.
|
|
This function must guarantee that all PCI read and write operations are serialized.
|
|
|
|
If any reserved bits in Address are set, then ASSERT().
|
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
|
|
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
|
|
@param AndData The value to AND with the PCI configuration register.
|
|
|
|
@return The value written to the PCI configuration register.
|
|
|
|
**/
|
|
UINT32
|
|
EFIAPI
|
|
PciSegmentAnd32 (
|
|
IN UINT64 Address,
|
|
IN UINT32 AndData
|
|
)
|
|
{
|
|
UINTN Count;
|
|
PCI_SEGMENT_INFO *SegmentInfo;
|
|
|
|
SegmentInfo = GetPciSegmentInfo (&Count);
|
|
return MmioAnd32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData);
|
|
}
|
|
|
|
/**
|
|
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
|
|
followed a bitwise OR with another 32-bit value.
|
|
|
|
Reads the 32-bit PCI configuration register specified by Address,
|
|
performs a bitwise AND between the read result and the value specified by AndData,
|
|
performs a bitwise OR between the result of the AND operation and the value specified by OrData,
|
|
and writes the result to the 32-bit PCI configuration register specified by Address.
|
|
The value written to the PCI configuration register is returned.
|
|
This function must guarantee that all PCI read and write operations are serialized.
|
|
|
|
If any reserved bits in Address are set, then ASSERT().
|
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
|
|
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
|
|
@param AndData The value to AND with the PCI configuration register.
|
|
@param OrData The value to OR with the PCI configuration register.
|
|
|
|
@return The value written to the PCI configuration register.
|
|
|
|
**/
|
|
UINT32
|
|
EFIAPI
|
|
PciSegmentAndThenOr32 (
|
|
IN UINT64 Address,
|
|
IN UINT32 AndData,
|
|
IN UINT32 OrData
|
|
)
|
|
{
|
|
UINTN Count;
|
|
PCI_SEGMENT_INFO *SegmentInfo;
|
|
|
|
SegmentInfo = GetPciSegmentInfo (&Count);
|
|
return MmioAndThenOr32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData, OrData);
|
|
}
|
|
|
|
/**
|
|
Reads a bit field of a PCI configuration register.
|
|
|
|
Reads the bit field in a 32-bit PCI configuration register. The bit field is
|
|
specified by the StartBit and the EndBit. The value of the bit field is
|
|
returned.
|
|
|
|
If any reserved bits in Address are set, then ASSERT().
|
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
If StartBit is greater than 31, then ASSERT().
|
|
If EndBit is greater than 31, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
|
|
@param Address PCI configuration register to read.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..31.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..31.
|
|
|
|
@return The value of the bit field read from the PCI configuration register.
|
|
|
|
**/
|
|
UINT32
|
|
EFIAPI
|
|
PciSegmentBitFieldRead32 (
|
|
IN UINT64 Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit
|
|
)
|
|
{
|
|
UINTN Count;
|
|
PCI_SEGMENT_INFO *SegmentInfo;
|
|
|
|
SegmentInfo = GetPciSegmentInfo (&Count);
|
|
return MmioBitFieldRead32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit);
|
|
}
|
|
|
|
/**
|
|
Writes a bit field to a PCI configuration register.
|
|
|
|
Writes Value to the bit field of the PCI configuration register. The bit
|
|
field is specified by the StartBit and the EndBit. All other bits in the
|
|
destination PCI configuration register are preserved. The new value of the
|
|
32-bit register is returned.
|
|
|
|
If any reserved bits in Address are set, then ASSERT().
|
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
If StartBit is greater than 31, then ASSERT().
|
|
If EndBit is greater than 31, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
|
@param Address PCI configuration register to write.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..31.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..31.
|
|
@param Value New value of the bit field.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT32
|
|
EFIAPI
|
|
PciSegmentBitFieldWrite32 (
|
|
IN UINT64 Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit,
|
|
IN UINT32 Value
|
|
)
|
|
{
|
|
UINTN Count;
|
|
PCI_SEGMENT_INFO *SegmentInfo;
|
|
|
|
SegmentInfo = GetPciSegmentInfo (&Count);
|
|
return MmioBitFieldWrite32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, Value);
|
|
}
|
|
|
|
/**
|
|
Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
|
|
writes the result back to the bit field in the 32-bit port.
|
|
|
|
Reads the 32-bit PCI configuration register specified by Address, performs a
|
|
bitwise OR between the read result and the value specified by
|
|
OrData, and writes the result to the 32-bit PCI configuration register
|
|
specified by Address. The value written to the PCI configuration register is
|
|
returned. This function must guarantee that all PCI read and write operations
|
|
are serialized. Extra left bits in OrData are stripped.
|
|
|
|
If any reserved bits in Address are set, then ASSERT().
|
|
If StartBit is greater than 31, then ASSERT().
|
|
If EndBit is greater than 31, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
|
@param Address PCI configuration register to write.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..31.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..31.
|
|
@param OrData The value to OR with the PCI configuration register.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT32
|
|
EFIAPI
|
|
PciSegmentBitFieldOr32 (
|
|
IN UINT64 Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit,
|
|
IN UINT32 OrData
|
|
)
|
|
{
|
|
UINTN Count;
|
|
PCI_SEGMENT_INFO *SegmentInfo;
|
|
|
|
SegmentInfo = GetPciSegmentInfo (&Count);
|
|
return MmioBitFieldOr32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, OrData);
|
|
}
|
|
|
|
/**
|
|
Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
|
|
AND, and writes the result back to the bit field in the 32-bit register.
|
|
|
|
|
|
Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
|
|
AND between the read result and the value specified by AndData, and writes the result
|
|
to the 32-bit PCI configuration register specified by Address. The value written to
|
|
the PCI configuration register is returned. This function must guarantee that all PCI
|
|
read and write operations are serialized. Extra left bits in AndData are stripped.
|
|
If any reserved bits in Address are set, then ASSERT().
|
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
If StartBit is greater than 31, then ASSERT().
|
|
If EndBit is greater than 31, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
|
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..31.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..31.
|
|
@param AndData The value to AND with the PCI configuration register.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT32
|
|
EFIAPI
|
|
PciSegmentBitFieldAnd32 (
|
|
IN UINT64 Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit,
|
|
IN UINT32 AndData
|
|
)
|
|
{
|
|
UINTN Count;
|
|
PCI_SEGMENT_INFO *SegmentInfo;
|
|
|
|
SegmentInfo = GetPciSegmentInfo (&Count);
|
|
return MmioBitFieldAnd32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData);
|
|
}
|
|
|
|
/**
|
|
Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
|
|
bitwise OR, and writes the result back to the bit field in the
|
|
32-bit port.
|
|
|
|
Reads the 32-bit PCI configuration register specified by Address, performs a
|
|
bitwise AND followed by a bitwise OR between the read result and
|
|
the value specified by AndData, and writes the result to the 32-bit PCI
|
|
configuration register specified by Address. The value written to the PCI
|
|
configuration register is returned. This function must guarantee that all PCI
|
|
read and write operations are serialized. Extra left bits in both AndData and
|
|
OrData are stripped.
|
|
|
|
If any reserved bits in Address are set, then ASSERT().
|
|
If StartBit is greater than 31, then ASSERT().
|
|
If EndBit is greater than 31, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
|
@param Address PCI configuration register to write.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..31.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..31.
|
|
@param AndData The value to AND with the PCI configuration register.
|
|
@param OrData The value to OR with the result of the AND operation.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT32
|
|
EFIAPI
|
|
PciSegmentBitFieldAndThenOr32 (
|
|
IN UINT64 Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit,
|
|
IN UINT32 AndData,
|
|
IN UINT32 OrData
|
|
)
|
|
{
|
|
UINTN Count;
|
|
PCI_SEGMENT_INFO *SegmentInfo;
|
|
|
|
SegmentInfo = GetPciSegmentInfo (&Count);
|
|
return MmioBitFieldAndThenOr32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData, OrData);
|
|
}
|
|
|
|
/**
|
|
Reads a range of PCI configuration registers into a caller supplied buffer.
|
|
|
|
Reads the range of PCI configuration registers specified by StartAddress and
|
|
Size into the buffer specified by Buffer. This function only allows the PCI
|
|
configuration registers from a single PCI function to be read. Size is
|
|
returned. When possible 32-bit PCI configuration read cycles are used to read
|
|
from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit
|
|
and 16-bit PCI configuration read cycles may be used at the beginning and the
|
|
end of the range.
|
|
|
|
If any reserved bits in StartAddress are set, then ASSERT().
|
|
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
|
|
If Size > 0 and Buffer is NULL, then ASSERT().
|
|
|
|
@param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
|
|
Function and Register.
|
|
@param Size Size in bytes of the transfer.
|
|
@param Buffer Pointer to a buffer receiving the data read.
|
|
|
|
@return Size
|
|
|
|
**/
|
|
UINTN
|
|
EFIAPI
|
|
PciSegmentReadBuffer (
|
|
IN UINT64 StartAddress,
|
|
IN UINTN Size,
|
|
OUT VOID *Buffer
|
|
)
|
|
{
|
|
UINTN ReturnValue;
|
|
UINTN Count;
|
|
PCI_SEGMENT_INFO *SegmentInfo;
|
|
UINTN Address;
|
|
|
|
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
|
|
|
|
SegmentInfo = GetPciSegmentInfo (&Count);
|
|
Address = PciSegmentLibGetEcamAddress (StartAddress, SegmentInfo, Count);
|
|
|
|
if (Size == 0) {
|
|
return 0;
|
|
}
|
|
|
|
ASSERT (Buffer != NULL);
|
|
|
|
//
|
|
// Save Size for return
|
|
//
|
|
ReturnValue = Size;
|
|
|
|
if ((Address & BIT0) != 0) {
|
|
//
|
|
// Read a byte if StartAddress is byte aligned
|
|
//
|
|
*(volatile UINT8 *)Buffer = MmioRead8 (Address);
|
|
Address += sizeof (UINT8);
|
|
Size -= sizeof (UINT8);
|
|
Buffer = (UINT8 *)Buffer + 1;
|
|
}
|
|
|
|
if ((Size >= sizeof (UINT16)) && ((Address & BIT1) != 0)) {
|
|
//
|
|
// Read a word if StartAddress is word aligned
|
|
//
|
|
WriteUnaligned16 (Buffer, MmioRead16 (Address));
|
|
Address += sizeof (UINT16);
|
|
Size -= sizeof (UINT16);
|
|
Buffer = (UINT16 *)Buffer + 1;
|
|
}
|
|
|
|
while (Size >= sizeof (UINT32)) {
|
|
//
|
|
// Read as many double words as possible
|
|
//
|
|
WriteUnaligned32 (Buffer, MmioRead32 (Address));
|
|
Address += sizeof (UINT32);
|
|
Size -= sizeof (UINT32);
|
|
Buffer = (UINT32 *)Buffer + 1;
|
|
}
|
|
|
|
if (Size >= sizeof (UINT16)) {
|
|
//
|
|
// Read the last remaining word if exist
|
|
//
|
|
WriteUnaligned16 (Buffer, MmioRead16 (Address));
|
|
Address += sizeof (UINT16);
|
|
Size -= sizeof (UINT16);
|
|
Buffer = (UINT16 *)Buffer + 1;
|
|
}
|
|
|
|
if (Size >= sizeof (UINT8)) {
|
|
//
|
|
// Read the last remaining byte if exist
|
|
//
|
|
*(volatile UINT8 *)Buffer = MmioRead8 (Address);
|
|
}
|
|
|
|
return ReturnValue;
|
|
}
|
|
|
|
/**
|
|
Copies the data in a caller supplied buffer to a specified range of PCI
|
|
configuration space.
|
|
|
|
Writes the range of PCI configuration registers specified by StartAddress and
|
|
Size from the buffer specified by Buffer. This function only allows the PCI
|
|
configuration registers from a single PCI function to be written. Size is
|
|
returned. When possible 32-bit PCI configuration write cycles are used to
|
|
write from StartAddress to StartAddress + Size. Due to alignment restrictions,
|
|
8-bit and 16-bit PCI configuration write cycles may be used at the beginning
|
|
and the end of the range.
|
|
|
|
If any reserved bits in StartAddress are set, then ASSERT().
|
|
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
|
|
If Size > 0 and Buffer is NULL, then ASSERT().
|
|
|
|
@param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
|
|
Function and Register.
|
|
@param Size Size in bytes of the transfer.
|
|
@param Buffer Pointer to a buffer containing the data to write.
|
|
|
|
@return The parameter of Size.
|
|
|
|
**/
|
|
UINTN
|
|
EFIAPI
|
|
PciSegmentWriteBuffer (
|
|
IN UINT64 StartAddress,
|
|
IN UINTN Size,
|
|
IN VOID *Buffer
|
|
)
|
|
{
|
|
UINTN ReturnValue;
|
|
UINTN Count;
|
|
PCI_SEGMENT_INFO *SegmentInfo;
|
|
UINTN Address;
|
|
|
|
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
|
|
|
|
SegmentInfo = GetPciSegmentInfo (&Count);
|
|
Address = PciSegmentLibGetEcamAddress (StartAddress, SegmentInfo, Count);
|
|
|
|
if (Size == 0) {
|
|
return 0;
|
|
}
|
|
|
|
ASSERT (Buffer != NULL);
|
|
|
|
//
|
|
// Save Size for return
|
|
//
|
|
ReturnValue = Size;
|
|
|
|
if ((Address & BIT0) != 0) {
|
|
//
|
|
// Write a byte if StartAddress is byte aligned
|
|
//
|
|
MmioWrite8 (Address, *(UINT8 *)Buffer);
|
|
Address += sizeof (UINT8);
|
|
Size -= sizeof (UINT8);
|
|
Buffer = (UINT8 *)Buffer + 1;
|
|
}
|
|
|
|
if ((Size >= sizeof (UINT16)) && ((Address & BIT1) != 0)) {
|
|
//
|
|
// Write a word if StartAddress is word aligned
|
|
//
|
|
MmioWrite16 (Address, ReadUnaligned16 (Buffer));
|
|
Address += sizeof (UINT16);
|
|
Size -= sizeof (UINT16);
|
|
Buffer = (UINT16 *)Buffer + 1;
|
|
}
|
|
|
|
while (Size >= sizeof (UINT32)) {
|
|
//
|
|
// Write as many double words as possible
|
|
//
|
|
MmioWrite32 (Address, ReadUnaligned32 (Buffer));
|
|
Address += sizeof (UINT32);
|
|
Size -= sizeof (UINT32);
|
|
Buffer = (UINT32 *)Buffer + 1;
|
|
}
|
|
|
|
if (Size >= sizeof (UINT16)) {
|
|
//
|
|
// Write the last remaining word if exist
|
|
//
|
|
MmioWrite16 (Address, ReadUnaligned16 (Buffer));
|
|
Address += sizeof (UINT16);
|
|
Size -= sizeof (UINT16);
|
|
Buffer = (UINT16 *)Buffer + 1;
|
|
}
|
|
|
|
if (Size >= sizeof (UINT8)) {
|
|
//
|
|
// Write the last remaining byte if exist
|
|
//
|
|
MmioWrite8 (Address, *(UINT8 *)Buffer);
|
|
}
|
|
|
|
return ReturnValue;
|
|
}
|