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2069a63a8e
There are a number of mostly older guests such as RHEL-7 which do not support 5-level paging. This patch adds support for switching from 5-level paging mode back to 4-level paging mode. This is done in PEI, after inspecting the address space needed (installed memory and reservations configured via fw_cfg). By default small guests (which need less than 1 TB) will use 4-level paging mode. There is a fw_cfg override though, so it is possible to force the one or the other this way: qemu-system-x86_64 -fw_cfg name=opt/org.tianocode/PagingLevel,string=5 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
77 lines
1.7 KiB
NASM
77 lines
1.7 KiB
NASM
;------------------------------------------------------------------------------
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; @file
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;
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; Switch from 5-level paging mode to 4-level paging mode.
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;
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; This assumes everything (code, stack, page tables) is in 32-bit
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; address space. Which is true for PEI phase even in X64 builds
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; because low memory is used for early firmware setup.
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;
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; This also assumes the standard ResetVector GDT is active.
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;
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;------------------------------------------------------------------------------
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SECTION .text
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BITS 64
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global ASM_PFX(Switch4Level)
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ASM_PFX(Switch4Level):
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; save regs
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push rax
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push rbx
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push rcx
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push rdx
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; cs:ip for long mode
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lea rax, [rel Switch4Level64]
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mov rbx, 0x3800000000 ; LINEAR_CODE64_SEL << 32
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or rax, rbx
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push rax
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; cs:ip for 32-bit mode
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lea rax, [rel Switch4Level32]
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mov rbx, 0x1000000000 ; LINEAR_CODE_SEL << 32
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or rax, rbx
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push rax
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; enter 32-bit mode
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retf
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Switch4Level64:
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; restore regs
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pop rdx
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pop rcx
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pop rbx
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pop rax
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ret
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BITS 32
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Switch4Level32:
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; disable paging
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mov eax, cr0
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btc eax, 31 ; clear PG
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mov cr0, eax
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; disable 5-level paging
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mov eax, cr4
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btc eax, 12 ; clear la57
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mov cr4, eax
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; fixup cr3 (dereference 5th level)
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mov eax, cr3
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mov eax, [ eax ]
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and eax, 0xfffff000
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mov cr3, eax
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; enable paging
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mov eax, cr0
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bts eax, 31 ; set PG
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mov cr0, eax
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; back to long mode
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retf
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