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20dd836214
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3223 In the current design, memory protection is not available till CpuDxe is loaded. To resolve this, introduce CpuArchLib to move the CPU Architectural initialization to DxeCore. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Vitaly Cheptsov <vit9696@protonmail.com> Signed-off-by: Marvin Häuser <mhaeuser@posteo.de>
45 lines
1.2 KiB
NASM
45 lines
1.2 KiB
NASM
;------------------------------------------------------------------------------
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;*
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;* Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR>
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;* SPDX-License-Identifier: BSD-2-Clause-Patent
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;*
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;* CpuAsm.nasm
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;*
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;* Abstract:
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;*
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;------------------------------------------------------------------------------
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DEFAULT REL
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SECTION .text
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;------------------------------------------------------------------------------
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; VOID
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; SetCodeSelector (
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; UINT16 Selector
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; );
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;------------------------------------------------------------------------------
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global ASM_PFX(SetCodeSelector)
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ASM_PFX(SetCodeSelector):
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push rcx
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lea rax, [setCodeSelectorLongJump]
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push rax
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retfq
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setCodeSelectorLongJump:
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ret
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;------------------------------------------------------------------------------
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; VOID
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; SetDataSelectors (
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; UINT16 Selector
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; );
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;------------------------------------------------------------------------------
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global ASM_PFX(SetDataSelectors)
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ASM_PFX(SetDataSelectors):
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o16 mov ss, cx
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o16 mov ds, cx
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o16 mov es, cx
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o16 mov fs, cx
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o16 mov gs, cx
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ret
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