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20dd836214
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3223 In the current design, memory protection is not available till CpuDxe is loaded. To resolve this, introduce CpuArchLib to move the CPU Architectural initialization to DxeCore. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Vitaly Cheptsov <vit9696@protonmail.com> Signed-off-by: Marvin Häuser <mhaeuser@posteo.de>
34 lines
840 B
C
34 lines
840 B
C
/** @file
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Return Paging attribute.
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Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "CpuPageTable.h"
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/**
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Get paging details.
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@param PagingContextData The paging context.
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@param PageTableBase Return PageTableBase field.
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@param Attributes Return Attributes field.
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**/
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VOID
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GetPagingDetails (
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IN PAGE_TABLE_LIB_PAGING_CONTEXT_DATA *PagingContextData,
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OUT UINTN **PageTableBase OPTIONAL,
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OUT UINT32 **Attributes OPTIONAL
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)
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{
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if (PageTableBase != NULL) {
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*PageTableBase = &PagingContextData->X64.PageTableBase;
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}
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if (Attributes != NULL) {
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*Attributes = &PagingContextData->X64.Attributes;
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}
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}
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