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0f9283429d
Add a macro USE_5_LEVEL_PAGE_TABLE to determine whether to create 5 level page table. If macro USE_5_LEVEL_PAGE_TABLE is defined, PML5Table is created at (4G-12K), while PML4Table is at (4G-16K). In runtime check, if 5level paging is supported, use PML5Table, otherwise, use PML4Table. If macro USE_5_LEVEL_PAGE_TABLE is not defined, to save space, 5level paging is not created, and 4level paging is at (4G-12K) and be used. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Catharine West <catharine.west@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
45 lines
1.3 KiB
NASM
45 lines
1.3 KiB
NASM
;------------------------------------------------------------------------------
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; @file
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; Sets the CR3 register for 64-bit paging
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;
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; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;------------------------------------------------------------------------------
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BITS 32
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;
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; Modified: EAX
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;
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SetCr3ForPageTables64:
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;
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; These pages are built into the ROM image in X64/PageTables.asm
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;
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%ifdef USE_5_LEVEL_PAGE_TABLE
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mov eax, 0
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cpuid
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cmp eax, 07h ; check if basic CPUID leaf contains leaf 07
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jb NotSupport5LevelPaging ; 5level paging not support, downgrade to 4level paging
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mov eax, 07h ; check cpuid leaf 7, subleaf 0
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mov ecx, 0
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cpuid
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bt ecx, 16 ; [Bits 16] Supports 5-level paging if 1.
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jnc NotSupport5LevelPaging ; 5level paging not support, downgrade to 4level paging
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mov eax, ADDR_OF(Pml5)
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mov cr3, eax
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mov eax, cr4
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bts eax, 12 ; Set LA57=1.
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mov cr4, eax
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jmp SetCr3Done
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NotSupport5LevelPaging:
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%endif
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mov eax, ADDR_OF(Pml4)
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mov cr3, eax
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SetCr3Done:
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OneTimeCallRet SetCr3ForPageTables64
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