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https://github.com/acidanthera/audk.git
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a21a3438f7
The BaseMemEncryptSevLib functionality was updated to rely on the use of the OVMF/SEV workarea to check for SEV guests. However, this area is only updated when running the X64 OVMF build, not the hybrid Ia32/X64 build. Base SEV support is allowed under the Ia32/X64 build, but it now fails to boot as a result of the change. Update the ResetVector code to check for SEV features when built for 32-bit mode, not just 64-bit mode (requiring updates to both the Ia32 and Ia32X64 fdf files). Fixes: f1d1c337e7c0575da7fd248b2dd9cffc755940df Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Michael Roth <michael.roth@amd.com> Cc: Min Xu <min.m.xu@intel.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
128 lines
2.9 KiB
NASM
128 lines
2.9 KiB
NASM
;------------------------------------------------------------------------------
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; @file
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; Main routine of the pre-SEC code up through the jump into SEC
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;
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; Copyright (c) 2008 - 2009, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;------------------------------------------------------------------------------
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BITS 16
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;
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; Modified: EBX, ECX, EDX, EBP
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;
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; @param[in,out] RAX/EAX Initial value of the EAX register
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; (BIST: Built-in Self Test)
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; @param[in,out] DI 'BP': boot-strap processor, or
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; 'AP': application processor
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; @param[out] RBP/EBP Address of Boot Firmware Volume (BFV)
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; @param[out] DS Selector allowing flat access to all addresses
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; @param[out] ES Selector allowing flat access to all addresses
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; @param[out] FS Selector allowing flat access to all addresses
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; @param[out] GS Selector allowing flat access to all addresses
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; @param[out] SS Selector allowing flat access to all addresses
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;
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; @return None This routine jumps to SEC and does not return
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;
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Main16:
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OneTimeCall EarlyInit16
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;
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; Transition the processor from 16-bit real mode to 32-bit flat mode
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;
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OneTimeCall TransitionFromReal16To32BitFlat
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BITS 32
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; Clear the WorkArea header. The SEV probe routines will populate the
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; work area when detected.
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mov byte[WORK_AREA_GUEST_TYPE], 0
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%ifdef ARCH_X64
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jmp SearchBfv
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;
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; Entry point of Main32
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;
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Main32:
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OneTimeCall InitTdx
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SearchBfv:
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%endif
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;
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; Search for the Boot Firmware Volume (BFV)
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;
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OneTimeCall Flat32SearchForBfvBase
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;
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; EBP - Start of BFV
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;
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;
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; Search for the SEC entry point
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;
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OneTimeCall Flat32SearchForSecEntryPoint
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;
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; ESI - SEC Core entry point
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; EBP - Start of BFV
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;
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%ifdef ARCH_IA32
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;
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; SEV support can be built and run using the Ia32/X64 split environment.
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; Set the OVMF/SEV work area as appropriate.
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;
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OneTimeCall CheckSevFeatures
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;
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; Restore initial EAX value into the EAX register
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;
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mov eax, esp
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;
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; Jump to the 32-bit SEC entry point
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;
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jmp esi
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%else
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;
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; Transition the processor from 32-bit flat mode to 64-bit flat mode
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;
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OneTimeCall Transition32FlatTo64Flat
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BITS 64
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;
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; Some values were calculated in 32-bit mode. Make sure the upper
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; 32-bits of 64-bit registers are zero for these values.
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;
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mov rax, 0x00000000ffffffff
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and rsi, rax
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and rbp, rax
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and rsp, rax
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;
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; RSI - SEC Core entry point
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; RBP - Start of BFV
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;
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;
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; Restore initial EAX value into the RAX register
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;
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mov rax, rsp
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;
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; Jump to the 64-bit SEC entry point
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;
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jmp rsi
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%endif
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