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9344f09215
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
46 lines
1.1 KiB
C
46 lines
1.1 KiB
C
/** @file
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64-bit arithmetic right shift function for IA-32.
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Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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/**
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Shifts a 64-bit integer right between 0 and 63 bits. The high bits
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are filled with original integer's bit 63. The shifted value is returned.
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This function shifts the 64-bit value Operand to the right by Count bits. The
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high Count bits are set to bit 63 of Operand. The shifted value is returned.
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@param Operand The 64-bit operand to shift right.
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@param Count The number of bits to shift right.
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@return Operand arithmetically shifted right by Count.
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**/
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UINT64
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EFIAPI
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InternalMathARShiftU64 (
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IN UINT64 Operand,
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IN UINTN Count
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)
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{
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_asm {
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mov cl, byte ptr [Count]
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mov eax, dword ptr [Operand + 4]
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cdq
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test cl, 32
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jnz L0
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mov edx, eax
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mov eax, dword ptr [Operand + 0]
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L0:
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shrd eax, edx, cl
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sar edx, cl
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}
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}
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