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b26f0cf9ee
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
99 lines
3.0 KiB
C
99 lines
3.0 KiB
C
/** @file
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Macro and type definitions corresponding to the QEMU fw_cfg interface.
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Refer to "docs/specs/fw_cfg.txt" in the QEMU source directory.
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Copyright (c) 2011 - 2013, Intel Corporation. All rights reserved.<BR>
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Copyright (C) 2013 - 2017, Red Hat, Inc.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __FW_CFG_H__
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#define __FW_CFG_H__
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#include <Base.h>
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//
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// The size, in bytes, of names of firmware configuration files, including at
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// least one terminating NUL byte.
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//
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#define QEMU_FW_CFG_FNAME_SIZE 56
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//
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// If the following bit is set in the UINT32 fw_cfg revision / feature bitmap
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// -- read from key 0x0001 with the basic IO Port or MMIO method --, then the
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// DMA interface is available.
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//
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#define FW_CFG_F_DMA BIT1
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//
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// Macros for the FW_CFG_DMA_ACCESS.Control bitmap (in native encoding).
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//
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#define FW_CFG_DMA_CTL_ERROR BIT0
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#define FW_CFG_DMA_CTL_READ BIT1
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#define FW_CFG_DMA_CTL_SKIP BIT2
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#define FW_CFG_DMA_CTL_SELECT BIT3
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#define FW_CFG_DMA_CTL_WRITE BIT4
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//
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// The fw_cfg registers can be found at these IO Ports, on the IO-mapped
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// platforms (Ia32 and X64).
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//
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#define FW_CFG_IO_SELECTOR 0x510
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#define FW_CFG_IO_DATA 0x511
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#define FW_CFG_IO_DMA_ADDRESS 0x514
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//
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// Numerically defined keys.
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//
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typedef enum {
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QemuFwCfgItemSignature = 0x0000,
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QemuFwCfgItemInterfaceVersion = 0x0001,
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QemuFwCfgItemSystemUuid = 0x0002,
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QemuFwCfgItemRamSize = 0x0003,
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QemuFwCfgItemGraphicsEnabled = 0x0004,
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QemuFwCfgItemSmpCpuCount = 0x0005,
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QemuFwCfgItemMachineId = 0x0006,
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QemuFwCfgItemKernelAddress = 0x0007,
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QemuFwCfgItemKernelSize = 0x0008,
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QemuFwCfgItemKernelCommandLine = 0x0009,
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QemuFwCfgItemInitrdAddress = 0x000a,
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QemuFwCfgItemInitrdSize = 0x000b,
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QemuFwCfgItemBootDevice = 0x000c,
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QemuFwCfgItemNumaData = 0x000d,
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QemuFwCfgItemBootMenu = 0x000e,
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QemuFwCfgItemMaximumCpuCount = 0x000f,
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QemuFwCfgItemKernelEntry = 0x0010,
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QemuFwCfgItemKernelData = 0x0011,
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QemuFwCfgItemInitrdData = 0x0012,
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QemuFwCfgItemCommandLineAddress = 0x0013,
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QemuFwCfgItemCommandLineSize = 0x0014,
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QemuFwCfgItemCommandLineData = 0x0015,
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QemuFwCfgItemKernelSetupAddress = 0x0016,
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QemuFwCfgItemKernelSetupSize = 0x0017,
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QemuFwCfgItemKernelSetupData = 0x0018,
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QemuFwCfgItemFileDir = 0x0019,
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QemuFwCfgItemX86AcpiTables = 0x8000,
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QemuFwCfgItemX86SmbiosTables = 0x8001,
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QemuFwCfgItemX86Irq0Override = 0x8002,
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QemuFwCfgItemX86E820Table = 0x8003,
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QemuFwCfgItemX86HpetData = 0x8004,
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} FIRMWARE_CONFIG_ITEM;
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//
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// Communication structure for the DMA access method. All fields are encoded in
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// big endian.
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//
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#pragma pack (1)
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typedef struct {
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UINT32 Control;
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UINT32 Length;
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UINT64 Address;
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} FW_CFG_DMA_ACCESS;
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#pragma pack ()
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#endif
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