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RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429 Intel's Trust Domain Extensions (Intel TDX) refers to an Intel technology that extends Virtual Machines Extensions (VMX) and Multi-Key Total Memory Encryption (MKTME) with a new kind of virutal machines guest called a Trust Domain (TD). A TD is desinged to run in a CPU mode that protects the confidentiality of TD memory contents and the TD's CPU state from other software, including the hosting Virtual-Machine Monitor (VMM), unless explicitly shared by the TD itself. Note: Intel TDX is only available on X64, so the Tdx related changes are in X64 path. In IA32 path, there may be null stub to make the build success. This patch includes below major changes. 1. Ia32/IntelTdx.asm IntelTdx.asm includes below routines used in ResetVector - IsTdx Check if the running system is Tdx guest. - InitTdxWorkarea It initialize the TDX_WORK_AREA. Because it is called by both BSP and APs and to avoid the race condition, only BSP can initialize the WORK_AREA. AP will wait until the field of TDX_WORK_AREA_PGTBL_READY is set. - ReloadFlat32 After reset all CPUs in TDX are initialized to 32-bit protected mode. But GDT register is not set. So this routine loads the GDT then jump to Flat 32 protected mode again. - InitTdx This routine wrap above 3 routines together to do Tdx initialization in ResetVector phase. - IsTdxEnabled It is a OneTimeCall to probe if TDX is enabled by checking the CC_WORK_AREA. - CheckTdxFeaturesBeforeBuildPagetables This routine is called to check if it is Non-TDX guest, TDX-Bsp or TDX-APs. Because in TDX guest all the initialization is done by BSP (including the page tables). APs should not build the tables. - TdxPostBuildPageTables It is called after Page Tables are built by BSP. byte[TDX_WORK_AREA_PGTBL_READY] is set by BSP to indicate APs can leave spin and go. 2. Ia32/PageTables64.asm As described above only the TDX BSP build the page tables. So PageTables64.asm is updated to make sure only TDX BSP build the PageTables. TDX APs will skip the page table building and set Cr3 directly. 3. Ia16/ResetVectorVtf0.asm In Tdx all CPUs "reset" to run on 32-bit protected mode with flat descriptor (paging disabled). But in Non-Td guest the initial state of CPUs is 16-bit real mode. To resolve this conflict, BITS 16/32 is used in the ResetVectorVtf0.asm. It checks the 32-bit protected mode or 16-bit real mode, then jump to the corresponding entry point. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
126 lines
4.7 KiB
Plaintext
126 lines
4.7 KiB
Plaintext
;------------------------------------------------------------------------------
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; @file
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; This file includes all other code files to assemble the reset vector code
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;
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; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
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; Copyright (c) 2020, Advanced Micro Devices, Inc. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;------------------------------------------------------------------------------
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;
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; If neither ARCH_IA32 nor ARCH_X64 are defined, then try to include
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; Base.h to use the C pre-processor to determine the architecture.
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;
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%ifndef ARCH_IA32
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%ifndef ARCH_X64
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#include <Base.h>
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#if defined (MDE_CPU_IA32)
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%define ARCH_IA32
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#elif defined (MDE_CPU_X64)
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%define ARCH_X64
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#endif
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%endif
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%endif
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%ifdef ARCH_IA32
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%ifdef ARCH_X64
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%error "Only one of ARCH_IA32 or ARCH_X64 can be defined."
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%endif
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%elifdef ARCH_X64
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%else
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%error "Either ARCH_IA32 or ARCH_X64 must be defined."
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%endif
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%include "CommonMacros.inc"
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%include "PostCodes.inc"
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%ifdef DEBUG_PORT80
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%include "Port80Debug.asm"
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%elifdef DEBUG_SERIAL
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%include "SerialDebug.asm"
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%else
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%include "DebugDisabled.asm"
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%endif
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%include "Ia32/SearchForBfvBase.asm"
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%include "Ia32/SearchForSecEntry.asm"
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%define WORK_AREA_GUEST_TYPE (FixedPcdGet32 (PcdOvmfWorkAreaBase))
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%ifdef ARCH_X64
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#include <AutoGen.h>
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%if (FixedPcdGet32 (PcdOvmfSecPageTablesSize) != 0x6000)
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%error "This implementation inherently depends on PcdOvmfSecPageTablesSize"
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%endif
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%if (FixedPcdGet32 (PcdOvmfSecGhcbPageTableSize) != 0x1000)
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%error "This implementation inherently depends on PcdOvmfSecGhcbPageTableSize"
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%endif
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%if (FixedPcdGet32 (PcdOvmfSecGhcbSize) != 0x2000)
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%error "This implementation inherently depends on PcdOvmfSecGhcbSize"
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%endif
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%if ((FixedPcdGet32 (PcdOvmfSecGhcbBase) >> 21) != \
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((FixedPcdGet32 (PcdOvmfSecGhcbBase) + FixedPcdGet32 (PcdOvmfSecGhcbSize) - 1) >> 21))
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%error "This implementation inherently depends on PcdOvmfSecGhcbBase not straddling a 2MB boundary"
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%endif
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%define TDX_BFV_RAW_DATA_OFFSET FixedPcdGet32 (PcdBfvRawDataOffset)
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%define TDX_BFV_RAW_DATA_SIZE FixedPcdGet32 (PcdBfvRawDataSize)
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%define TDX_BFV_MEMORY_BASE FixedPcdGet32 (PcdBfvBase)
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%define TDX_BFV_MEMORY_SIZE FixedPcdGet32 (PcdBfvRawDataSize)
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%define TDX_CFV_RAW_DATA_OFFSET FixedPcdGet32 (PcdCfvRawDataOffset)
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%define TDX_CFV_RAW_DATA_SIZE FixedPcdGet32 (PcdCfvRawDataSize)
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%define TDX_CFV_MEMORY_BASE FixedPcdGet32 (PcdCfvBase),
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%define TDX_CFV_MEMORY_SIZE FixedPcdGet32 (PcdCfvRawDataSize),
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%define TDX_HEAP_STACK_BASE FixedPcdGet32 (PcdOvmfSecPeiTempRamBase)
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%define TDX_HEAP_STACK_SIZE FixedPcdGet32 (PcdOvmfSecPeiTempRamSize)
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%define TDX_HOB_MEMORY_BASE FixedPcdGet32 (PcdOvmfSecGhcbBase)
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%define TDX_HOB_MEMORY_SIZE FixedPcdGet32 (PcdOvmfSecGhcbSize)
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%define TDX_INIT_MEMORY_BASE FixedPcdGet32 (PcdOvmfWorkAreaBase)
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%define TDX_INIT_MEMORY_SIZE (FixedPcdGet32 (PcdOvmfWorkAreaSize) + FixedPcdGet32 (PcdOvmfSecGhcbBackupSize))
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%define OVMF_PAGE_TABLE_BASE FixedPcdGet32 (PcdOvmfSecPageTablesBase)
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%define OVMF_PAGE_TABLE_SIZE FixedPcdGet32 (PcdOvmfSecPageTablesSize)
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%define TDX_WORK_AREA_PGTBL_READY (FixedPcdGet32 (PcdOvmfWorkAreaBase) + 4)
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%define TDX_WORK_AREA_GPAW (FixedPcdGet32 (PcdOvmfWorkAreaBase) + 8)
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%define PT_ADDR(Offset) (FixedPcdGet32 (PcdOvmfSecPageTablesBase) + (Offset))
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%define GHCB_PT_ADDR (FixedPcdGet32 (PcdOvmfSecGhcbPageTableBase))
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%define GHCB_BASE (FixedPcdGet32 (PcdOvmfSecGhcbBase))
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%define GHCB_SIZE (FixedPcdGet32 (PcdOvmfSecGhcbSize))
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%define SEV_ES_WORK_AREA (FixedPcdGet32 (PcdSevEsWorkAreaBase))
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%define SEV_ES_WORK_AREA_RDRAND (FixedPcdGet32 (PcdSevEsWorkAreaBase) + 8)
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%define SEV_ES_WORK_AREA_ENC_MASK (FixedPcdGet32 (PcdSevEsWorkAreaBase) + 16)
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%define SEV_ES_VC_TOP_OF_STACK (FixedPcdGet32 (PcdOvmfSecPeiTempRamBase) + FixedPcdGet32 (PcdOvmfSecPeiTempRamSize))
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%include "X64/IntelTdxMetadata.asm"
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%include "Ia32/Flat32ToFlat64.asm"
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%include "Ia32/AmdSev.asm"
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%include "Ia32/PageTables64.asm"
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%include "Ia32/IntelTdx.asm"
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%endif
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%include "Ia16/Real16ToFlat32.asm"
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%include "Ia16/Init16.asm"
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%include "Main.asm"
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%define SEV_ES_AP_RESET_IP FixedPcdGet32 (PcdSevEsWorkAreaBase)
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%define SEV_LAUNCH_SECRET_BASE FixedPcdGet32 (PcdSevLaunchSecretBase)
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%define SEV_LAUNCH_SECRET_SIZE FixedPcdGet32 (PcdSevLaunchSecretSize)
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%define SEV_FW_HASH_BLOCK_BASE FixedPcdGet32 (PcdQemuHashTableBase)
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%define SEV_FW_HASH_BLOCK_SIZE FixedPcdGet32 (PcdQemuHashTableSize)
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%include "Ia16/ResetVectorVtf0.asm"
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