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4123bd7bf7
Use mov instead of movw. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16531 6f19259b-4bc3-4df7-8a09-765794883524
432 lines
9.6 KiB
ArmAsm
432 lines
9.6 KiB
ArmAsm
#------------------------------------------------------------------------------
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#
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# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php.
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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# Module Name:
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#
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# AsmFuncs.S
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#
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# Abstract:
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#
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# Debug interrupt handle functions.
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#
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#------------------------------------------------------------------------------
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#include "DebugException.h"
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ASM_GLOBAL ASM_PFX(InterruptProcess)
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ASM_GLOBAL ASM_PFX(Exception0Handle)
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ASM_GLOBAL ASM_PFX(ExceptionStubHeaderSize)
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ASM_GLOBAL ASM_PFX(TimerInterruptHandle)
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ASM_GLOBAL ASM_PFX(CommonEntry)
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.macro AGENT_HANDLER_SIGNATURE
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.byte 0x41, 0x47, 0x54, 0x48 # AGENT_HANDLER_SIGNATURE SIGNATURE_32('A','G','T','H')
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.endm
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.data
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ASM_PFX(ExceptionStubHeaderSize): .long ASM_PFX(Exception1Handle) - ASM_PFX(Exception0Handle)
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.text
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AGENT_HANDLER_SIGNATURE
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ASM_PFX(Exception0Handle):
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cli
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pushq %rcx
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mov $0, %rcx
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jmp ASM_PFX(CommonEntry)
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AGENT_HANDLER_SIGNATURE
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ASM_PFX(Exception1Handle):
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cli
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pushq %rcx
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mov $1, %rcx
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jmp ASM_PFX(CommonEntry)
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AGENT_HANDLER_SIGNATURE
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ASM_PFX(Exception2Handle):
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cli
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pushq %rcx
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mov $2, %rcx
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jmp ASM_PFX(CommonEntry)
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AGENT_HANDLER_SIGNATURE
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ASM_PFX(Exception3Handle):
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cli
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pushq %rcx
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mov $3, %rcx
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jmp ASM_PFX(CommonEntry)
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AGENT_HANDLER_SIGNATURE
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ASM_PFX(Exception4Handle):
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cli
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pushq %rcx
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mov $4, %rcx
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jmp ASM_PFX(CommonEntry)
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AGENT_HANDLER_SIGNATURE
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ASM_PFX(Exception5Handle):
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cli
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pushq %rcx
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mov $5, %rcx
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jmp ASM_PFX(CommonEntry)
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AGENT_HANDLER_SIGNATURE
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ASM_PFX(Exception6Handle):
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cli
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pushq %rcx
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mov $6, %rcx
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jmp ASM_PFX(CommonEntry)
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AGENT_HANDLER_SIGNATURE
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ASM_PFX(Exception7Handle):
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cli
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pushq %rcx
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mov $7, %rcx
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jmp ASM_PFX(CommonEntry)
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AGENT_HANDLER_SIGNATURE
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ASM_PFX(Exception8Handle):
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cli
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pushq %rcx
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mov $8, %rcx
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jmp ASM_PFX(CommonEntry)
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AGENT_HANDLER_SIGNATURE
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ASM_PFX(Exception9Handle):
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cli
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pushq %rcx
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mov $9, %rcx
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jmp ASM_PFX(CommonEntry)
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AGENT_HANDLER_SIGNATURE
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ASM_PFX(Exception10Handle):
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cli
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pushq %rcx
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mov $10, %rcx
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jmp ASM_PFX(CommonEntry)
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AGENT_HANDLER_SIGNATURE
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ASM_PFX(Exception11Handle):
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cli
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pushq %rcx
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mov $11, %rcx
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jmp ASM_PFX(CommonEntry)
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AGENT_HANDLER_SIGNATURE
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ASM_PFX(Exception12Handle):
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cli
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pushq %rcx
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mov $12, %rcx
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jmp ASM_PFX(CommonEntry)
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AGENT_HANDLER_SIGNATURE
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ASM_PFX(Exception13Handle):
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cli
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pushq %rcx
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mov $13, %rcx
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jmp ASM_PFX(CommonEntry)
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AGENT_HANDLER_SIGNATURE
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ASM_PFX(Exception14Handle):
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cli
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pushq %rcx
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mov $14, %rcx
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jmp ASM_PFX(CommonEntry)
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AGENT_HANDLER_SIGNATURE
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ASM_PFX(Exception15Handle):
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cli
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pushq %rcx
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mov $15, %rcx
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jmp ASM_PFX(CommonEntry)
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AGENT_HANDLER_SIGNATURE
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ASM_PFX(Exception16Handle):
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cli
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pushq %rcx
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mov $16, %rcx
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jmp ASM_PFX(CommonEntry)
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AGENT_HANDLER_SIGNATURE
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ASM_PFX(Exception17Handle):
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cli
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pushq %rcx
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mov $17, %rcx
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jmp ASM_PFX(CommonEntry)
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AGENT_HANDLER_SIGNATURE
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ASM_PFX(Exception18Handle):
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cli
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pushq %rcx
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mov $18, %rcx
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jmp ASM_PFX(CommonEntry)
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AGENT_HANDLER_SIGNATURE
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ASM_PFX(Exception19Handle):
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cli
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pushq %rcx
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mov $19, %rcx
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jmp ASM_PFX(CommonEntry)
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AGENT_HANDLER_SIGNATURE
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ASM_PFX(TimerInterruptHandle):
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cli
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pushq %rcx
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mov $32, %rcx
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jmp ASM_PFX(CommonEntry)
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ASM_PFX(CommonEntry):
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#---------------------------------------;
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# CommonInterruptEntry ;
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#---------------------------------------;
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# The follow algorithm is used for the common interrupt routine.
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#
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# +---------------------+ <-- 16-byte aligned ensured by processor
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# + Old SS +
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# +---------------------+
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# + Old RSP +
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# +---------------------+
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# + RFlags +
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# +---------------------+
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# + CS +
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# +---------------------+
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# + RIP +
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# +---------------------+
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# + Error Code +
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# +---------------------+
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# + RCX / Vector Number +
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# +---------------------+
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# + RBP +
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# +---------------------+ <-- RBP, 16-byte aligned
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#
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# We need to determine if any extra data was pushed by the exception
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cmpq $DEBUG_EXCEPT_DOUBLE_FAULT, %rcx
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je NoExtrPush
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cmpq $DEBUG_EXCEPT_INVALID_TSS, %rcx
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je NoExtrPush
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cmpq $DEBUG_EXCEPT_SEG_NOT_PRESENT, %rcx
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je NoExtrPush
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cmpq $DEBUG_EXCEPT_STACK_FAULT, %rcx
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je NoExtrPush
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cmpq $DEBUG_EXCEPT_GP_FAULT, %rcx
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je NoExtrPush
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cmpq $DEBUG_EXCEPT_PAGE_FAULT, %rcx
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je NoExtrPush
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cmpq $DEBUG_EXCEPT_ALIGNMENT_CHECK, %rcx
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je NoExtrPush
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pushq (%rsp)
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movq $0, 8(%rsp)
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NoExtrPush:
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#
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# All interrupt handlers are invoked through interrupt gates, so
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# IF flag automatically cleared at the entry point
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pushq %rbp
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movq %rsp, %rbp
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#
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# Since here the stack pointer is 16-byte aligned, so
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# EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
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# is 16-byte aligned
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#
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## UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
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pushq %r15
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pushq %r14
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pushq %r13
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pushq %r12
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pushq %r11
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pushq %r10
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pushq %r9
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pushq %r8
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movq %cr8, %r8
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pushq %r8
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## UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
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pushq %rax
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pushq %rbx
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pushq 8(%rbp) # original rcx
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pushq %rdx
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pushq 48(%rbp) # original rsp
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pushq (%rbp) # original rbp
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pushq %rsi
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pushq %rdi
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## UINT64 Cr0, Cr1, Cr2, Cr3, Cr4;
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movq %cr4, %rax
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orq $0x208, %rax
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movq %rax, %cr4
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pushq %rax
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movq %cr3, %rax
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pushq %rax
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movq %cr2, %rax
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pushq %rax
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xorq %rax, %rax
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pushq %rax
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movq %cr0, %rax
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pushq %rax
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## UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
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xorq %rax, %rax # set rax to 0
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movzwq 56(%rbp), %rax
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# movq %ss, %rax
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pushq %rax
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movzwq 32(%rbp), %rax
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# movq %cs, %rax
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pushq %rax
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mov %ds, %rax
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pushq %rax
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mov %es, %rax
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pushq %rax
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mov %fs, %rax
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pushq %rax
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mov %gs, %rax
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pushq %rax
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## UINT64 Rip;
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pushq 24(%rbp)
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## UINT64 Gdtr[2], Idtr[2];
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subq $16, %rsp
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sidt (%rsp)
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subq $16, %rsp
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sgdt (%rsp)
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## UINT64 Ldtr, Tr;
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xorq %rax, %rax
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strw %ax
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pushq %rax
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sldtw %ax
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pushq %rax
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## UINT64 RFlags;
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pushq 40(%rbp)
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## UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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movq %dr7, %rax
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pushq %rax
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## clear Dr7 while executing debugger itself
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xorq %rax, %rax
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movq %rax, %dr7
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movq %dr6, %rax
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pushq %rax
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## insure all status bits in dr6 are clear...
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xorq %rax, %rax
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movq %rax, %dr6
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movq %dr3, %rax
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pushq %rax
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movq %dr2, %rax
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pushq %rax
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movq %dr1, %rax
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pushq %rax
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movq %dr0, %rax
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pushq %rax
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## FX_SAVE_STATE_X64 FxSaveState;
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subq $512, %rsp
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movq %rsp, %rdi
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.byte 0x0f, 0xae, 0b00000111
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## save the exception data;
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pushq 16(%rbp)
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## Clear Direction Flag
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cld
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## Prepare parameter and call
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# movq 8(%rbp), %rcx
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movq %rsp, %rdx
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movq %rcx, %r15 # save vector in r15
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#
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# Per X64 calling convention, allocate maximum parameter stack space
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# and make sure RSP is 16-byte aligned
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#
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subq $(32 + 8), %rsp
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call ASM_PFX(InterruptProcess)
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addq $(32 + 8), %rsp
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## skip the exception data;
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addq $8, %rsp
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## FX_SAVE_STATE_X64 FxSaveState;
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movq %rsp, %rsi
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.byte 0x0f, 0xae, 0b00001110
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addq $512, %rsp
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## UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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popq %rax
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movq %rax, %dr0
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popq %rax
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movq %rax, %dr1
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popq %rax
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movq %rax, %dr2
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popq %rax
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movq %rax, %dr3
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## skip restore of dr6. We cleared dr6 during the context save.
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addq $8, %rsp
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popq %rax
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movq %rax, %dr7
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## UINT64 RFlags;
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popq 40(%rbp)
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## UINT64 Ldtr, Tr;
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## UINT64 Gdtr[2], Idtr[2];
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## Best not let anyone mess with these particular registers...
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addq $48, %rsp
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## UINT64 Rip;
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popq 24(%rbp)
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## UINT64 Gs, Fs, Es, Ds, Cs, Ss;
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popq %rax
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# mov gs, rax ; not for gs
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popq %rax
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# mov fs, rax ; not for fs
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# (X64 will not use fs and gs, so we do not restore it)
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popq %rax
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mov %rax, %es
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popq %rax
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mov %rax, %ds
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popq 32(%rbp)
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popq 56(%rbp)
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## UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
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popq %rax
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movq %rax, %cr0
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addq $8, %rsp
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popq %rax
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movq %rax, %cr2
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popq %rax
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movq %rax, %cr3
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popq %rax
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movq %rax, %cr4
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## UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
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## UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
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popq %rdi
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popq %rsi
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addq $8, %rsp
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addq $8, %rsp
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popq %rdx
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popq %rcx
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popq %rbx
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popq %rax
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popq %r8
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movq %r8, %cr8
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popq %r8
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popq %r9
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popq %r10
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popq %r11
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popq %r12
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popq %r13
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popq %r14
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popq %r15
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movq %rbp, %rsp
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popq %rbp
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addq $16, %rsp
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iretq
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