mirror of https://github.com/acidanthera/audk.git
275 lines
10 KiB
C
275 lines
10 KiB
C
/** @file
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Header file for Industry MMC 4.2 spec.
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Copyright (c) 2013-2015 Intel Corporation.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _MMC_H
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#define _MMC_H
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#pragma pack(1)
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//
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//Command definition
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//
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#define CMD0 0
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#define CMD1 1
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#define CMD2 2
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#define CMD3 3
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#define CMD4 4
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#define CMD6 6
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#define CMD7 7
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#define CMD8 8
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#define CMD9 9
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#define CMD10 10
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#define CMD11 11
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#define CMD12 12
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#define CMD13 13
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#define CMD14 14
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#define CMD15 15
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#define CMD16 16
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#define CMD17 17
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#define CMD18 18
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#define CMD19 19
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#define CMD20 20
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#define CMD23 23
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#define CMD24 24
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#define CMD25 25
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#define CMD26 26
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#define CMD27 27
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#define CMD28 28
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#define CMD29 29
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#define CMD30 30
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#define CMD35 35
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#define CMD36 36
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#define CMD38 38
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#define CMD39 39
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#define CMD40 40
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#define CMD42 42
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#define CMD55 55
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#define CMD56 56
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#define GO_IDLE_STATE CMD0
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#define SEND_OP_COND CMD1
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#define ALL_SEND_CID CMD2
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#define SET_RELATIVE_ADDR CMD3
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#define SET_DSR CMD4
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#define SWITCH CMD6
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#define SELECT_DESELECT_CARD CMD7
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#define SEND_EXT_CSD CMD8
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#define SEND_CSD CMD9
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#define SEND_CID CMD10
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#define READ_DAT_UNTIL_STOP CMD11
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#define STOP_TRANSMISSION CMD12
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#define SEND_STATUS CMD13
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#define BUSTEST_R CMD14
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#define GO_INACTIVE_STATE CMD15
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#define SET_BLOCKLEN CMD16
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#define READ_SINGLE_BLOCK CMD17
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#define READ_MULTIPLE_BLOCK CMD18
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#define BUSTEST_W CMD19
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#define WRITE_DAT_UNTIL_STOP CMD20
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#define SET_BLOCK_COUNT CMD23
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#define WRITE_BLOCK CMD24
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#define WRITE_MULTIPLE_BLOCK CMD25
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#define PROGRAM_CID CMD26
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#define PROGRAM_CSD CMD27
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#define SET_WRITE_PROT CMD28
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#define CLR_WRITE_PROT CMD29
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#define SEND_WRITE_PROT CMD30
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#define ERASE_GROUP_START CMD35
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#define ERASE_GROUP_END CMD36
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#define ERASE CMD38
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#define FAST_IO CMD39
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#define GO_IRQ_STATE CMD40
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#define LOCK_UNLOCK CMD42
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#define APP_CMD CMD55
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#define GEN_CMD CMD56
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#define CMD_INDEX_MASK 0x3F
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#define AUTO_CMD12_ENABLE BIT6
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#define AUTO_CMD23_ENABLE BIT7
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#define FREQUENCY_OD (400 * 1000)
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#define FREQUENCY_MMC_PP (26 * 1000 * 1000)
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#define FREQUENCY_MMC_PP_HIGH (52 * 1000 * 1000)
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#define DEFAULT_DSR_VALUE 0x404
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//
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//Registers definition
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//
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typedef struct {
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UINT32 Reserved0: 7; // 0
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UINT32 V170_V195: 1; // 1.70V - 1.95V
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UINT32 V200_V260: 7; // 2.00V - 2.60V
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UINT32 V270_V360: 9; // 2.70V - 3.60V
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UINT32 Reserved1: 5; // 0
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UINT32 AccessMode: 2; // 00b (byte mode), 10b (sector mode)
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UINT32 Busy: 1; // This bit is set to LOW if the card has not finished the power up routine
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}OCR;
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typedef struct {
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UINT8 NotUsed: 1; // 1
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UINT8 CRC: 7; // CRC7 checksum
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UINT8 MDT; // Manufacturing date
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UINT32 PSN; // Product serial number
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UINT8 PRV; // Product revision
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UINT8 PNM[6]; // Product name
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UINT16 OID; // OEM/Application ID
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UINT8 MID; // Manufacturer ID
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}CID;
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typedef struct {
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UINT8 NotUsed: 1; // 1 [0:0]
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UINT8 CRC: 7; // CRC [7:1]
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UINT8 ECC: 2; // ECC code [9:8]
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UINT8 FILE_FORMAT: 2; // File format [11:10]
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UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12]
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UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]
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UINT8 COPY: 1; // Copy flag (OTP) [14:14]
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UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15]
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UINT16 CONTENT_PROT_APP: 1; // Content protection application [16:16]
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UINT16 Reserved0: 4; // 0 [20:17]
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UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21]
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UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22]
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UINT16 R2W_FACTOR: 3; // Write speed factor [28:26]
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UINT16 DEFAULT_ECC: 2; // Manufacturer default ECC [30:29]
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UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31]
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UINT32 WP_GRP_SIZE: 5; // Write protect group size [36:32]
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UINT32 ERASE_GRP_MULT: 5; // Erase group size multiplier [41:37]
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UINT32 ERASE_GRP_SIZE: 5; // Erase group size [46:42]
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UINT32 C_SIZE_MULT: 3; // Device size multiplier [49:47]
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UINT32 VDD_W_CURR_MAX: 3; // Max. write current @ VDD max [52:50]
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UINT32 VDD_W_CURR_MIN: 3; // Max. write current @ VDD min [55:53]
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UINT32 VDD_R_CURR_MAX: 3; // Max. read current @ VDD max [58:56]
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UINT32 VDD_R_CURR_MIN: 3; // Max. read current @ VDD min [61:59]
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UINT32 C_SIZELow2: 2;// Device size [73:62]
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UINT32 C_SIZEHigh10: 10;// Device size [73:62]
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UINT32 Reserved1: 2; // 0 [75:74]
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UINT32 DSR_IMP: 1; // DSR implemented [76:76]
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UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77]
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UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78]
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UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79]
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UINT32 READ_BL_LEN: 4; // Max. read data block length [83:80]
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UINT32 CCC: 12;// Card command classes [95:84]
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UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96]
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UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
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UINT8 TAAC ; // Data read access-time 1 [119:112]
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UINT8 Reserved2: 2; // 0 [121:120]
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UINT8 SPEC_VERS: 4; // System specification version [125:122]
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UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126]
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}CSD;
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typedef struct {
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UINT8 Reserved0[181]; // 0 [0:180]
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UINT8 ERASED_MEM_CONT; // Erased Memory Content [181]
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UINT8 Reserved2; // Erased Memory Content [182]
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UINT8 BUS_WIDTH; // Bus Width Mode [183]
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UINT8 Reserved3; // 0 [184]
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UINT8 HS_TIMING; // High Speed Interface Timing [185]
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UINT8 Reserved4; // 0 [186]
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UINT8 POWER_CLASS; // Power Class [187]
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UINT8 Reserved5; // 0 [188]
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UINT8 CMD_SET_REV; // Command Set Revision [189]
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UINT8 Reserved6; // 0 [190]
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UINT8 CMD_SET; // Command Set [191]
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UINT8 EXT_CSD_REV; // Extended CSD Revision [192]
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UINT8 Reserved7; // 0 [193]
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UINT8 CSD_STRUCTURE; // CSD Structure Version [194]
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UINT8 Reserved8; // 0 [195]
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UINT8 CARD_TYPE; // Card Type [196]
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UINT8 Reserved9[3]; // 0 [199:197]
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UINT8 PWR_CL_52_195; // Power Class for 52MHz @ 1.95V [200]
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UINT8 PWR_CL_26_195; // Power Class for 26MHz @ 1.95V [201]
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UINT8 PWR_CL_52_360; // Power Class for 52MHz @ 3.6V [202]
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UINT8 PWR_CL_26_360; // Power Class for 26MHz @ 3.6V [203]
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UINT8 Reserved10; // 0 [204]
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UINT8 MIN_PERF_R_4_26; // Minimum Read Performance for 4bit @26MHz [205]
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UINT8 MIN_PERF_W_4_26; // Minimum Write Performance for 4bit @26MHz [206]
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UINT8 MIN_PERF_R_8_26_4_52; // Minimum Read Performance for 8bit @26MHz/4bit @52MHz [207]
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UINT8 MIN_PERF_W_8_26_4_52; // Minimum Write Performance for 8bit @26MHz/4bit @52MHz [208]
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UINT8 MIN_PERF_R_8_52; // Minimum Read Performance for 8bit @52MHz [209]
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UINT8 MIN_PERF_W_8_52; // Minimum Write Performance for 8bit @52MHz [210]
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UINT8 Reserved11; // 0 [211]
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UINT8 SEC_COUNT[4]; // Sector Count [215:212]
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UINT8 Reserved12[288]; // 0 [503:216]
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UINT8 S_CMD_SET; // Sector Count [504]
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UINT8 Reserved13[7]; // Sector Count [511:505]
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}EXT_CSD;
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//
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//Card Status definition
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//
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typedef struct {
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UINT32 Reserved0: 2; //Reserved for Manufacturer Test Mode
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UINT32 Reserved1: 2; //Reserved for Application Specific commands
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UINT32 Reserved2: 1; //
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UINT32 SAPP_CMD: 1; //
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UINT32 Reserved3: 1; //Reserved
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UINT32 SWITCH_ERROR: 1; //
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UINT32 READY_FOR_DATA: 1; //
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UINT32 CURRENT_STATE: 4; //
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UINT32 ERASE_RESET: 1; //
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UINT32 Reserved4: 1; //Reserved
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UINT32 WP_ERASE_SKIP: 1; //
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UINT32 CID_CSD_OVERWRITE: 1; //
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UINT32 OVERRUN: 1; //
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UINT32 UNDERRUN: 1; //
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UINT32 ERROR: 1; //
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UINT32 CC_ERROR: 1; //
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UINT32 CARD_ECC_FAILED: 1; //
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UINT32 ILLEGAL_COMMAND: 1; //
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UINT32 COM_CRC_ERROR: 1; //
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UINT32 LOCK_UNLOCK_FAILED: 1; //
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UINT32 CARD_IS_LOCKED: 1; //
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UINT32 WP_VIOLATION: 1; //
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UINT32 ERASE_PARAM: 1; //
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UINT32 ERASE_SEQ_ERROR: 1; //
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UINT32 BLOCK_LEN_ERROR: 1; //
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UINT32 ADDRESS_MISALIGN: 1; //
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UINT32 ADDRESS_OUT_OF_RANGE:1; //
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}CARD_STATUS;
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typedef struct {
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UINT32 CmdSet: 3;
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UINT32 Reserved0: 5;
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UINT32 Value: 8;
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UINT32 Index: 8;
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UINT32 Access: 2;
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UINT32 Reserved1: 6;
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}SWITCH_ARGUMENT;
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#define CommandSet_Mode 0
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#define SetBits_Mode 1
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#define ClearBits_Mode 2
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#define WriteByte_Mode 3
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#define Idle_STATE 0
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#define Ready_STATE 1
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#define Ident_STATE 2
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#define Stby_STATE 3
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#define Tran_STATE 4
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#define Data_STATE 5
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#define Rcv_STATE 6
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#define Prg_STATE 7
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#define Dis_STATE 8
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#define Btst_STATE 9
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#pragma pack()
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#endif
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