mirror of https://github.com/acidanthera/audk.git
240 lines
8.8 KiB
C
240 lines
8.8 KiB
C
/*++
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Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _SPIFlash_H_
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#define _SPIFlash_H_
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#include <Protocol/Spi.h>
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//EFI_STATUS SpiFlashLock(BOOLEAN Lock);
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//EFI_STATUS SpiFlashInit(void);
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typedef enum {
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EnumSpiFlashW25Q64,
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EnumSpiFlashAT25DF321A,
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EnumSpiFlashAT26DF321,
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EnumSpiFlashAT25DF641,
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EnumSpiFlashW25Q16,
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EnumSpiFlashW25Q32,
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EnumSpiFlashW25X32,
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EnumSpiFlashW25X64,
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EnumSpiFlashW25Q128,
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EnumSpiFlashMX25L16,
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EnumSpiFlashMX25L32,
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EnumSpiFlashMX25L64,
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EnumSpiFlashMX25L128,
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EnumSpiFlashMX25U6435F,
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EnumSpiFlashSST25VF016B,
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EnumSpiFlashSST25VF064C,
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EnumSpiFlashN25Q064,
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EnumSpiFlashM25PX16,
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EnumSpiFlashN25Q032,
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EnumSpiFlashM25PX32,
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EnumSpiFlashM25PX64,
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EnumSpiFlashN25Q128,
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EnumSpiFlashEN25Q16,
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EnumSpiFlashEN25Q32,
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EnumSpiFlashEN25Q64,
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EnumSpiFlashEN25Q128,
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EnumSpiFlashA25L016,
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EnumSpiFlashMax
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} SPI_FLASH_TYPES_SUPPORTED;
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//
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// Serial Flash VendorId and DeviceId
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//
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#define SF_VENDOR_ID_ATMEL 0x1F
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#define SF_DEVICE_ID0_AT26DF321 0x47
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#define SF_DEVICE_ID1_AT26DF321 0x00
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#define SF_DEVICE_ID0_AT25DF321A 0x47
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#define SF_DEVICE_ID1_AT25DF321A 0x01
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#define SF_DEVICE_ID0_AT25DF641 0x48
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#define SF_DEVICE_ID1_AT25DF641 0x00
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#define SF_VENDOR_ID_WINBOND 0xEF
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#define SF_DEVICE_ID0_W25XXX 0x30
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#define SF_DEVICE_ID1_W25X32 0x16
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#define SF_DEVICE_ID1_W25X64 0x17
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#define SF_DEVICE_ID0_W25QXX 0x40
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#define SF_DEVICE_ID1_W25Q16 0x15
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#define SF_DEVICE_ID1_W25Q32 0x16
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#define SF_DEVICE_ID1_W25Q64 0x17
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#define SF_DEVICE_ID1_W25Q128 0x18
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#define SF_VENDOR_ID_MACRONIX 0xC2
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#define SF_DEVICE_ID0_MX25LXX 0x20
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#define SF_DEVICE_ID1_MX25L16 0x15
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#define SF_DEVICE_ID1_MX25L32 0x16
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#define SF_DEVICE_ID1_MX25L64 0x17
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#define SF_DEVICE_ID1_MX25L128 0x18
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#define SF_DEVICE_ID0_MX25UXX 0x25
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#define SF_DEVICE_ID1_MX25U6435F 0x37
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#define SF_VENDOR_ID_NUMONYX 0x20
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#define SF_DEVICE_ID0_N25Q064 0xBB
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#define SF_DEVICE_ID1_N25Q064 0x17
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#define SF_DEVICE_ID0_M25PXXX 0x71
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#define SF_DEVICE_ID0_N25QXXX 0xBA
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#define SF_DEVICE_ID1_M25PX16 0x15
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#define SF_DEVICE_ID1_N25Q032 0x16
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#define SF_DEVICE_ID1_M25PX32 0x16
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#define SF_DEVICE_ID1_M25PX64 0x17
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#define SF_DEVICE_ID1_N25Q128 0x18
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#define SF_VENDOR_ID_SST 0xBF
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#define SF_DEVICE_ID0_SST25VF0XXX 0x25
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#define SF_DEVICE_ID1_SST25VF016B 0x41
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#define SF_DEVICE_ID1_SST25VF064C 0x4B
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#define SF_VENDOR_ID_EON 0x1C
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#define SF_DEVICE_ID0_EN25QXX 0x30
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#define SF_DEVICE_ID1_EN25Q16 0x15
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#define SF_DEVICE_ID1_EN25Q32 0x16
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#define SF_DEVICE_ID1_EN25Q64 0x17
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#define SF_DEVICE_ID1_EN25Q128 0x18
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#define SF_VENDOR_ID_AMIC 0x37
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#define SF_DEVICE_ID0_A25L016 0x30
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#define SF_DEVICE_ID1_A25L016 0x15
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#define ATMEL_AT26DF321_SIZE 0x00400000
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#define ATMEL_AT25DF321A_SIZE 0x00400000
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#define ATMEL_AT25DF641_SIZE 0x00800000
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#define WINBOND_W25X32_SIZE 0x00400000
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#define WINBOND_W25X64_SIZE 0x00800000
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#define WINBOND_W25Q16_SIZE 0x00200000
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#define WINBOND_W25Q32_SIZE 0x00400000
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#define WINBOND_W25Q64_SIZE 0x00800000
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#define WINBOND_W25Q128_SIZE 0x01000000
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#define SST_SST25VF016B_SIZE 0x00200000
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#define SST_SST25VF064C_SIZE 0x00800000
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#define MACRONIX_MX25L16_SIZE 0x00200000
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#define MACRONIX_MX25L32_SIZE 0x00400000
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#define MACRONIX_MX25L64_SIZE 0x00800000
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#define MACRONIX_MX25U64_SIZE 0x00800000
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#define MACRONIX_MX25L128_SIZE 0x01000000
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#define NUMONYX_M25PX16_SIZE 0x00400000
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#define NUMONYX_N25Q032_SIZE 0x00400000
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#define NUMONYX_M25PX32_SIZE 0x00400000
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#define NUMONYX_M25PX64_SIZE 0x00800000
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#define NUMONYX_N25Q064_SIZE 0x00800000
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#define NUMONYX_N25Q128_SIZE 0x01000000
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#define EON_EN25Q16_SIZE 0x00200000
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#define EON_EN25Q32_SIZE 0x00400000
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#define EON_EN25Q64_SIZE 0x00800000
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#define EON_EN25Q128_SIZE 0x01000000
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#define AMIC_A25L16_SIZE 0x00200000
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#define SF_VENDOR_ID_SST 0xBF
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#define SF_DEVICE_ID0_25LF080A 0x25
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#define SF_DEVICE_ID1_25LF080A 0x8E
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#define SF_DEVICE_ID0_25VF016B 0x25
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#define SF_DEVICE_ID1_25VF016B 0x41
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#define SF_VENDOR_ID_ATMEL 0x1F
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#define SF_DEVICE_ID0_AT26DF321 0x47
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#define SF_DEVICE_ID1_AT26DF321 0x00
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#define SF_VENDOR_ID_STM 0x20
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#define SF_DEVICE_ID0_M25P32 0x20
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#define SF_DEVICE_ID1_M25P32 0x16
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#define SF_VENDOR_ID_WINBOND 0xEF
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#define SF_DEVICE_ID0_W25XXX 0x30
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#define SF_DEVICE_ID1_W25X80 0x14
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#define SF_DEVICE_ID1_W25X16 0x15
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#define SF_DEVICE_ID1_W25X32 0x16
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#define SF_DEVICE_ID1_W25X64 0x17
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#define SF_VENDOR_ID_MX 0xC2
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#define SF_DEVICE_ID0_25L1605A 0x20
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#define SF_DEVICE_ID1_25L1605A 0x15
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#define SF_VENDOR_ID_NUMONYX 0x20
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#define SF_DEVICE_ID0_M25PX16 0x71
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#define SF_DEVICE_ID1_M25PX16 0x15
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#define SST_25LF080A_SIZE 0x00100000
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#define SST_25LF016B_SIZE 0x00200000
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#define ATMEL_AT26DF321_SIZE 0x00400000
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#define STM_M25P32_SIZE 0x00400000
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#define WINBOND_W25X80_SIZE 0x00100000
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#define WINBOND_W25X16_SIZE 0x00200000
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#define WINBOND_W25X32_SIZE 0x00400000
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#define WINBOND_W25X64_SIZE 0x00800000
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#define MX_25L1605A_SIZE 0x00200000
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//
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// Physical Sector Size on the Serial Flash device
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//
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#define SF_SECTOR_SIZE 0x1000
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#define SF_BLOCK_SIZE 0x8000
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//
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// Serial Flash Status Register definitions
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//
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#define SF_SR_BUSY 0x01 // Indicates if internal write operation is in progress
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#define SF_SR_WEL 0x02 // Indicates if device is memory write enabled
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#define SF_SR_BP0 0x04 // Block protection bit 0
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#define SF_SR_BP1 0x08 // Block protection bit 1
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#define SF_SR_BP2 0x10 // Block protection bit 2
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#define SF_SR_BP3 0x20 // Block protection bit 3
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#define SF_SR_WPE 0x3C // Enable write protection on all blocks
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#define SF_SR_AAI 0x40 // Auto Address Increment Programming status
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#define SF_SR_BPL 0x80 // Block protection lock-down
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//
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// Operation Instruction definitions for the Serial Flash Device
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//
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#define SF_INST_WRSR 0x01 // Write Status Register
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#define SF_INST_PROG 0x02 // Byte Program
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#define SF_INST_READ 0x03 // Read
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#define SF_INST_WRDI 0x04 // Write Disable
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#define SF_INST_RDSR 0x05 // Read Status Register
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#define SF_INST_WREN 0x06 // Write Enable
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#define SF_INST_HS_READ 0x0B // High-speed Read
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#define SF_INST_SERASE 0x20 // Sector Erase (4KB)
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#define SF_INST_BERASE 0x52 // Block Erase (32KB)
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#define SF_INST_64KB_ERASE 0xD8 // Block Erase (64KB)
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#define SF_INST_EWSR 0x50 // Enable Write Status Register
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#define SF_INST_READ_ID 0xAB // Read ID
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#define SF_INST_JEDEC_READ_ID 0x9F // JEDEC Read ID
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#define SF_INST_DOFR 0x3B // Dual Output Fast Read
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#define SF_INST_SFDP 0x5A // Serial Flash Discovery Parameters
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#define SECTOR_SIZE_4KB 0x1000 // Common 4kBytes sector size
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#define SECTOR_SIZE_64KB 0x10000 // Common 64kBytes sector size
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#define BLOCK_SIZE_64KB 0x00010000 // Common 64kBytes block size
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#define MAX_FWH_SIZE 0x00100000 // 8Mbit (Note that this can also be used for the 4Mbit )
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//
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// Prefix Opcode Index on the host SPI controller
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//
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typedef enum {
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SPI_WREN, // Prefix Opcode 0: Write Enable
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SPI_EWSR, // Prefix Opcode 1: Enable Write Status Register
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} PREFIX_OPCODE_INDEX;
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//
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// Opcode Menu Index on the host SPI controller
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//
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typedef enum {
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SPI_READ_ID, // Opcode 0: READ ID, Read cycle with address
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SPI_READ, // Opcode 1: READ, Read cycle with address
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SPI_RDSR, // Opcode 2: Read Status Register, No address
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SPI_WRDI_SFDP, // Opcode 3: Write Disable or Discovery Parameters, No address
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SPI_SERASE, // Opcode 4: Sector Erase (4KB), Write cycle with address
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SPI_BERASE, // Opcode 5: Block Erase (32KB), Write cycle with address
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SPI_PROG, // Opcode 6: Byte Program, Write cycle with address
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SPI_WRSR, // Opcode 7: Write Status Register, No address
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} SPI_OPCODE_INDEX;
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#endif
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