mirror of https://github.com/acidanthera/audk.git
267 lines
7.4 KiB
C
267 lines
7.4 KiB
C
/** @file
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The definition for UHCI register operation routines.
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Copyright (c) 2007, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _EFI_UHCI_QUEUE_H_
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#define _EFI_UHCI_QUEUE_H_
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//
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// Macroes used to set various links in UHCI's driver.
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// In this UHCI driver, QH's horizontal link always pointers to other QH,
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// and its vertical link always pointers to TD. TD's next pointer always
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// pointers to other sibling TD. Frame link always pointers to QH because
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// ISO transfer isn't supported.
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//
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// We should use UINT32 to access these pointers to void race conditions
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// with hardware.
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//
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#define QH_HLINK(Pointer, Terminate) \
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(((UINT32) ((UINTN) (Pointer)) & 0xFFFFFFF0) | 0x02 | ((Terminate) ? 0x01 : 0))
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#define QH_VLINK(Pointer, Terminate) \
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(((UINT32) ((UINTN) (Pointer)) & 0xFFFFFFF0) | ((Terminate) ? 0x01 : 0))
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#define TD_LINK(Pointer, VertFirst, Terminate) \
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(((UINT32) ((UINTN) (Pointer)) & 0xFFFFFFF0) | \
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((VertFirst) ? 0x04 : 0) | ((Terminate) ? 0x01 : 0))
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#define LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
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#define UHCI_ADDR(QhOrTd) ((VOID *) (UINTN) ((QhOrTd) & 0xFFFFFFF0))
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#pragma pack(1)
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//
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// Both links in QH has this internal structure:
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// Next pointer: 28, Reserved: 2, NextIsQh: 1, Terminate: 1
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// This is the same as frame list entry.
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//
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typedef struct {
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UINT32 HorizonLink;
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UINT32 VerticalLink;
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} UHCI_QH_HW;
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//
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// Next link in TD has this internal structure:
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// Next pointer: 28, Reserved: 1, Vertical First: 1, NextIsQh: 1, Terminate: 1
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//
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typedef struct {
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UINT32 NextLink;
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UINT32 ActualLen : 11;
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UINT32 Reserved1 : 5;
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UINT32 Status : 8;
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UINT32 IntOnCpl : 1;
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UINT32 IsIsoch : 1;
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UINT32 LowSpeed : 1;
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UINT32 ErrorCount : 2;
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UINT32 ShortPacket : 1;
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UINT32 Reserved2 : 2;
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UINT32 PidCode : 8;
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UINT32 DeviceAddr : 7;
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UINT32 EndPoint : 4;
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UINT32 DataToggle : 1;
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UINT32 Reserved3 : 1;
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UINT32 MaxPacketLen: 11;
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UINT32 DataBuffer;
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} UHCI_TD_HW;
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#pragma pack()
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typedef struct _UHCI_TD_SW UHCI_TD_SW;
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typedef struct _UHCI_QH_SW UHCI_QH_SW;
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struct _UHCI_QH_SW {
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UHCI_QH_HW QhHw;
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UHCI_QH_SW *NextQh;
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UHCI_TD_SW *TDs;
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UINTN Interval;
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};
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struct _UHCI_TD_SW {
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UHCI_TD_HW TdHw;
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UHCI_TD_SW *NextTd;
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UINT8 *Data;
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UINT16 DataLen;
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};
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/**
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Link the TD To QH.
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@param Uhc The UHCI device.
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@param Qh The queue head for the TD to link to.
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@param Td The TD to link.
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**/
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VOID
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UhciLinkTdToQh (
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IN USB_HC_DEV *Uhc,
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IN UHCI_QH_SW *Qh,
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IN UHCI_TD_SW *Td
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);
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/**
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Unlink TD from the QH.
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@param Qh The queue head to unlink from.
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@param Td The TD to unlink.
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@return None.
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**/
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VOID
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UhciUnlinkTdFromQh (
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IN UHCI_QH_SW *Qh,
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IN UHCI_TD_SW *Td
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);
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/**
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Map address of request structure buffer.
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@param Uhc The UHCI device.
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@param Request The user request buffer.
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@param MappedAddr Mapped address of request.
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@param Map Identificaion of this mapping to return.
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@return EFI_SUCCESS Success.
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@return EFI_DEVICE_ERROR Fail to map the user request.
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**/
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EFI_STATUS
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UhciMapUserRequest (
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IN USB_HC_DEV *Uhc,
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IN OUT VOID *Request,
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OUT UINT8 **MappedAddr,
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OUT VOID **Map
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);
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/**
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Map address of user data buffer.
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@param Uhc The UHCI device.
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@param Direction Direction of the data transfer.
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@param Data The user data buffer.
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@param Len Length of the user data.
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@param PktId Packet identificaion.
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@param MappedAddr Mapped address to return.
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@param Map Identificaion of this mapping to return.
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@return EFI_SUCCESS Success.
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@return EFI_DEVICE_ERROR Fail to map the user data.
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**/
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EFI_STATUS
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UhciMapUserData (
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IN USB_HC_DEV *Uhc,
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IN EFI_USB_DATA_DIRECTION Direction,
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IN VOID *Data,
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IN OUT UINTN *Len,
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OUT UINT8 *PktId,
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OUT UINT8 **MappedAddr,
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OUT VOID **Map
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);
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/**
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Delete a list of TDs.
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@param Uhc The UHCI device.
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@param FirstTd TD link list head.
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@return None.
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**/
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VOID
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UhciDestoryTds (
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IN USB_HC_DEV *Uhc,
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IN UHCI_TD_SW *FirstTd
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);
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/**
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Create an initialize a new queue head.
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@param Uhc The UHCI device.
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@param Interval The polling interval for the queue.
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@return The newly created queue header.
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**/
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UHCI_QH_SW *
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UhciCreateQh (
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IN USB_HC_DEV *Uhc,
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IN UINTN Interval
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);
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/**
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Create Tds list for Control Transfer.
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@param Uhc The UHCI device.
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@param DeviceAddr The device address.
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@param DataPktId Packet Identification of Data Tds.
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@param Request A pointer to cpu memory address of request structure buffer to transfer.
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@param RequestPhy A pointer to pci memory address of request structure buffer to transfer.
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@param Data A pointer to cpu memory address of user data buffer to transfer.
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@param DataPhy A pointer to pci memory address of user data buffer to transfer.
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@param DataLen Length of user data to transfer.
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@param MaxPacket Maximum packet size for control transfer.
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@param IsLow Full speed or low speed.
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@return The Td list head for the control transfer.
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**/
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UHCI_TD_SW *
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UhciCreateCtrlTds (
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IN USB_HC_DEV *Uhc,
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IN UINT8 DeviceAddr,
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IN UINT8 DataPktId,
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IN UINT8 *Request,
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IN UINT8 *RequestPhy,
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IN UINT8 *Data,
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IN UINT8 *DataPhy,
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IN UINTN DataLen,
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IN UINT8 MaxPacket,
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IN BOOLEAN IsLow
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);
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/**
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Create Tds list for Bulk/Interrupt Transfer.
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@param Uhc USB_HC_DEV.
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@param DevAddr Address of Device.
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@param EndPoint Endpoint Number.
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@param PktId Packet Identification of Data Tds.
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@param Data A pointer to cpu memory address of user data buffer to transfer.
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@param DataPhy A pointer to pci memory address of user data buffer to transfer.
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@param DataLen Length of user data to transfer.
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@param DataToggle Data Toggle Pointer.
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@param MaxPacket Maximum packet size for Bulk/Interrupt transfer.
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@param IsLow Is Low Speed Device.
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@return The Tds list head for the bulk transfer.
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**/
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UHCI_TD_SW *
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UhciCreateBulkOrIntTds (
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IN USB_HC_DEV *Uhc,
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IN UINT8 DevAddr,
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IN UINT8 EndPoint,
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IN UINT8 PktId,
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IN UINT8 *Data,
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IN UINT8 *DataPhy,
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IN UINTN DataLen,
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IN OUT UINT8 *DataToggle,
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IN UINT8 MaxPacket,
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IN BOOLEAN IsLow
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);
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#endif
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