Jeff Fan 5f0a17d83a MdePkg/BaseSynchronizationLib: Add spin lock alignment for IA32/x64 ... From Intel(R) 64 and IA-32 Architectures Software Developer's Manual, one lock or semaphore is suggested to be present within a cache line. If the processors are based on Intel NetBurst microarchitecture, two cache lines are suggested. This could minimize the bus traffic required to service locks. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>		2016-04-05 14:07:15 +08:00
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InterlockedCompareExchange16.s	MdePkg: Convert non DOS format files to DOS format	2015-03-05 07:21:34 +00:00
InterlockedCompareExchange32.s	Minor grammatical work--mostly adding periods. Items with ONLY period added did not have the heading date changed, but Items with content changes had heading copyright dates updated. Sending separately a list of files missing Doxygen @param and @return information. (PENDING)	2010-06-25 21:56:02 +00:00
InterlockedCompareExchange64.s	Minor grammatical work--mostly adding periods. Items with ONLY period added did not have the heading date changed, but Items with content changes had heading copyright dates updated. Sending separately a list of files missing Doxygen @param and @return information. (PENDING)	2010-06-25 21:56:02 +00:00
InternalGetSpinLockProperties.c	MdePkg/BaseSynchronizationLib: Add spin lock alignment for IA32/x64	2016-04-05 14:07:15 +08:00
Synchronization.c	Minor grammatical work--mostly adding periods. Items with ONLY period added did not have the heading date changed, but Items with content changes had heading copyright dates updated. Sending separately a list of files missing Doxygen @param and @return information. (PENDING)	2010-06-25 21:56:02 +00:00