mirror of https://github.com/acidanthera/audk.git
82 lines
1.9 KiB
C
82 lines
1.9 KiB
C
/** @file
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Copyright (c) 2011-2014, ARM Limited. All rights reserved.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Base.h>
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#include <Library/ArmLib.h>
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#include <Library/ArmCpuLib.h>
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#include <Library/ArmGenericTimerCounterLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include <Chipset/ArmCortexA5x.h>
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VOID
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ArmCpuSetup (
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IN UINTN MpId
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)
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{
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// Check if Architectural Timer frequency is valid number (should not be 0)
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ASSERT (PcdGet32 (PcdArmArchTimerFreqInHz));
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ASSERT (ArmIsArchTimerImplemented () != 0);
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// Note: System Counter frequency can only be set in Secure privileged mode,
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// if security extensions are implemented.
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ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));
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if (ArmIsMpCore ()) {
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// Turn on SMP coherency
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ArmSetCpuExCrBit (A5X_FEATURE_SMP);
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}
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//
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// If CPU is CortexA57 r0p0 apply Errata: 806969
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//
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if ((ArmReadMidr () & ((ARM_CPU_TYPE_MASK << 4) | ARM_CPU_REV_MASK)) ==
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((ARM_CPU_TYPE_A57 << 4) | ARM_CPU_REV(0,0))) {
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// DisableLoadStoreWB
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ArmSetCpuActlrBit (1ULL << 49);
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}
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}
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VOID
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ArmCpuSetupSmpNonSecure (
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IN UINTN MpId
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)
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{
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}
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VOID
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EFIAPI
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ArmSetCpuExCrBit (
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IN UINT64 Bits
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)
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{
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UINT64 Value;
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Value = ArmReadCpuExCr ();
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Value |= Bits;
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ArmWriteCpuExCr (Value);
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}
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VOID
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EFIAPI
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ArmUnsetCpuExCrBit (
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IN UINT64 Bits
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)
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{
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UINT64 Value;
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Value = ArmReadCpuExCr ();
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Value &= ~Bits;
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ArmWriteCpuExCr (Value);
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}
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