mirror of https://github.com/acidanthera/audk.git
04c7a5febd
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1483 Due to the limited resource on the VTd DMA buffer size in the PEI phase, the driver will limit the maximum transfer block number for 48-bit addressing. According to PCDs: gIntelSiliconPkgTokenSpaceGuid.PcdVTdPeiDmaBufferSize|0x00400000 gIntelSiliconPkgTokenSpaceGuid.PcdVTdPeiDmaBufferSizeS3|0x00200000 The default buffer size allocated for IOMMU mapping is: * 4M bytes for non-S3 cases; * 2M bytes for S3 For ATA devices in 48-bit address mode, the maximum block number is currently set to 0xFFFF. For a device with block size equal to 512 bytes, the maximum buffer allowed for mapping within AhciPei driver will be close to 32M bytes. Thus, this commit will limit the 48-bit mode maximum block number to 0x800, which means 1M-byte maximum buffer for mapping when the block size of a device is 512 bytes. By doing so, potential failure on calls to the IOMMU 'Map' service can be avoided. Cc: Eric Dong <eric.dong@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> |
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| .. | ||
| AhciMode.c | ||
| AhciPei.c | ||
| AhciPei.h | ||
| AhciPei.inf | ||
| AhciPei.uni | ||
| AhciPeiExtra.uni | ||
| AhciPeiPassThru.c | ||
| AhciPeiPassThru.h | ||
| AhciPeiS3.c | ||
| AhciPeiStorageSecurity.c | ||
| AhciPeiStorageSecurity.h | ||
| DevicePath.c | ||
| DmaMem.c | ||