mirror of https://github.com/acidanthera/audk.git
109 lines
4.0 KiB
C
109 lines
4.0 KiB
C
/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#define PL301_QOS_TIDEMARK_MI_0 0x400
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#define PL301_QOS_ACCESSCONTROL_MI_0 0x404
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#define PL301_QOS_TIDEMARK_MI_1 0x420
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#define PL301_QOS_ACCESSCONTROL_MI_1 0x424
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#define PL301_QOS_TIDEMARK_MI_2 0x440
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#define PL301_QOS_ACCESSCONTROL_MI_2 0x444
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#define PL301_AR_ARB_MI_0 0x408
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#define PL301_AW_ARB_MI_0 0x40C
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#define PL301_AR_ARB_MI_1 0x428
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#define PL301_AW_ARB_MI_1 0x42C
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#define PL301_AR_ARB_MI_2 0x448
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#define PL301_AW_ARB_MI_2 0x44C
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#define PL301_MI_1_OFFSET 0x20
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#define PL301_MI_2_OFFSET 0x40
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#define PL301_MI_3_OFFSET 0x60
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#define PL301_MI_4_OFFSET 0x80
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#define PL301_MI_5_OFFSET 0xa0
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#define V2P_CA9_FAXI_MI0_TIDEMARK_VAL 0x6
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#define V2P_CA9_FAXI_MI0_ACCESSCNTRL_VAL 0x1
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#define V2P_CA9_FAXI_MI1_TIDEMARK_VAL 0x6
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#define V2P_CA9_FAXI_MI1_ACCESSCNTRL_VAL 0x1
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#define V2P_CA9_FAXI_MI2_TIDEMARK_VAL 0x6
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#define V2P_CA9_FAXI_MI2_ACCESSCNTRL_VAL 0x1
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#define FAxiWriteReg(reg,val) MmioWrite32(FAxiBase + reg, val)
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#define FAxiReadReg(reg) MmioRead32(FAxiBase + reg)
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// IN FAxiBase
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// Initialize PL301 Dynamic Memory Controller
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VOID PL301AxiInit(UINTN FAxiBase) {
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// Configure Tidemark Register for Master Port 0 (MI 0)
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FAxiWriteReg(PL301_QOS_TIDEMARK_MI_0, V2P_CA9_FAXI_MI0_TIDEMARK_VAL);
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// Configure the Access Control Register (MI 0)
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FAxiWriteReg(PL301_QOS_ACCESSCONTROL_MI_0, V2P_CA9_FAXI_MI0_ACCESSCNTRL_VAL);
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// MP0
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// Set priority for Read
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FAxiWriteReg(PL301_AR_ARB_MI_0, 0x00000100);
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FAxiWriteReg(PL301_AR_ARB_MI_0, 0x01000200);
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FAxiWriteReg(PL301_AR_ARB_MI_0, 0x02000200);
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FAxiWriteReg(PL301_AR_ARB_MI_0, 0x03000200);
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FAxiWriteReg(PL301_AR_ARB_MI_0, 0x04000200);
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// Set priority for Write
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FAxiWriteReg(PL301_AW_ARB_MI_0, 0x00000100);
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FAxiWriteReg(PL301_AW_ARB_MI_0, 0x01000200);
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FAxiWriteReg(PL301_AW_ARB_MI_0, 0x02000200);
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FAxiWriteReg(PL301_AW_ARB_MI_0, 0x03000200);
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FAxiWriteReg(PL301_AW_ARB_MI_0, 0x04000200);
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// MP1
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// Set priority for Read
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FAxiWriteReg(PL301_AR_ARB_MI_1, 0x00000100);
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FAxiWriteReg(PL301_AR_ARB_MI_1, 0x01000200);
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FAxiWriteReg(PL301_AR_ARB_MI_1, 0x02000200);
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FAxiWriteReg(PL301_AR_ARB_MI_1, 0x03000200);
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FAxiWriteReg(PL301_AR_ARB_MI_1, 0x04000200);
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// Set priority for Write
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FAxiWriteReg(PL301_AW_ARB_MI_1, 0x00000100);
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FAxiWriteReg(PL301_AW_ARB_MI_1, 0x01000200);
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FAxiWriteReg(PL301_AW_ARB_MI_1, 0x02000200);
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FAxiWriteReg(PL301_AW_ARB_MI_1, 0x03000200);
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FAxiWriteReg(PL301_AW_ARB_MI_1, 0x04000200);
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// MP2
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// Set priority for Read
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FAxiWriteReg(PL301_AR_ARB_MI_2, 0x00000100);
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FAxiWriteReg(PL301_AR_ARB_MI_2, 0x01000100);
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FAxiWriteReg(PL301_AR_ARB_MI_2, 0x02000100);
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FAxiWriteReg(PL301_AR_ARB_MI_2, 0x03000100);
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FAxiWriteReg(PL301_AR_ARB_MI_2, 0x04000100);
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// Set priority for Write
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FAxiWriteReg(PL301_AW_ARB_MI_2, 0x00000100);
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FAxiWriteReg(PL301_AW_ARB_MI_2, 0x01000200);
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FAxiWriteReg(PL301_AW_ARB_MI_2, 0x02000200);
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FAxiWriteReg(PL301_AW_ARB_MI_2, 0x03000200);
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FAxiWriteReg(PL301_AW_ARB_MI_2, 0x04000200);
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}
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