mirror of https://github.com/acidanthera/audk.git
474 lines
15 KiB
C
474 lines
15 KiB
C
/** @file
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PCI Host Bridge Library instance for pci-ecam-generic DT nodes
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Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <PiDxe.h>
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#include <Library/PciHostBridgeLib.h>
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#include <Library/DebugLib.h>
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#include <Library/DevicePathLib.h>
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#include <Library/DxeServicesTableLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PcdLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Protocol/FdtClient.h>
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#include <Protocol/PciRootBridgeIo.h>
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#include <Protocol/PciHostBridgeResourceAllocation.h>
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#pragma pack(1)
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typedef struct {
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ACPI_HID_DEVICE_PATH AcpiDevicePath;
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EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
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} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
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#pragma pack ()
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STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath = {
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{
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{
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ACPI_DEVICE_PATH,
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ACPI_DP,
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{
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(UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
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(UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
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}
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},
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EISA_PNP_ID(0x0A03),
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0
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},
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{
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END_DEVICE_PATH_TYPE,
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END_ENTIRE_DEVICE_PATH_SUBTYPE,
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{
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END_DEVICE_PATH_LENGTH,
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0
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}
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}
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};
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GLOBAL_REMOVE_IF_UNREFERENCED
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CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
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L"Mem", L"I/O", L"Bus"
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};
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//
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// We expect the "ranges" property of "pci-host-ecam-generic" to consist of
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// records like this.
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//
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#pragma pack (1)
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typedef struct {
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UINT32 Type;
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UINT64 ChildBase;
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UINT64 CpuBase;
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UINT64 Size;
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} DTB_PCI_HOST_RANGE_RECORD;
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#pragma pack ()
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#define DTB_PCI_HOST_RANGE_RELOCATABLE BIT31
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#define DTB_PCI_HOST_RANGE_PREFETCHABLE BIT30
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#define DTB_PCI_HOST_RANGE_ALIASED BIT29
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#define DTB_PCI_HOST_RANGE_MMIO32 BIT25
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#define DTB_PCI_HOST_RANGE_MMIO64 (BIT25 | BIT24)
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#define DTB_PCI_HOST_RANGE_IO BIT24
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#define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
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STATIC
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EFI_STATUS
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MapGcdMmioSpace (
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IN UINT64 Base,
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IN UINT64 Size
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)
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{
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EFI_STATUS Status;
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Status = gDS->AddMemorySpace (EfiGcdMemoryTypeMemoryMappedIo, Base, Size,
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EFI_MEMORY_UC);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR,
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"%a: failed to add GCD memory space for region [0x%Lx+0x%Lx)\n",
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__FUNCTION__, Base, Size));
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return Status;
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}
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Status = gDS->SetMemorySpaceAttributes (Base, Size, EFI_MEMORY_UC);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR,
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"%a: failed to set memory space attributes for region [0x%Lx+0x%Lx)\n",
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__FUNCTION__, Base, Size));
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}
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return Status;
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}
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STATIC
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EFI_STATUS
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ProcessPciHost (
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OUT UINT64 *IoBase,
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OUT UINT64 *IoSize,
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OUT UINT64 *Mmio32Base,
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OUT UINT64 *Mmio32Size,
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OUT UINT64 *Mmio64Base,
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OUT UINT64 *Mmio64Size,
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OUT UINT32 *BusMin,
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OUT UINT32 *BusMax
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)
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{
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FDT_CLIENT_PROTOCOL *FdtClient;
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INT32 Node;
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UINT64 ConfigBase, ConfigSize;
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CONST VOID *Prop;
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UINT32 Len;
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UINT32 RecordIdx;
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EFI_STATUS Status;
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UINT64 IoTranslation;
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UINT64 Mmio32Translation;
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UINT64 Mmio64Translation;
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//
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// The following output arguments are initialized only in
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// order to suppress '-Werror=maybe-uninitialized' warnings
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// *incorrectly* emitted by some gcc versions.
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//
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*IoBase = 0;
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*Mmio32Base = 0;
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*Mmio64Base = MAX_UINT64;
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*BusMin = 0;
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*BusMax = 0;
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//
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// *IoSize, *Mmio##Size and IoTranslation are initialized to zero because the
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// logic below requires it. However, since they are also affected by the issue
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// reported above, they are initialized early.
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//
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*IoSize = 0;
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*Mmio32Size = 0;
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*Mmio64Size = 0;
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IoTranslation = 0;
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Status = gBS->LocateProtocol (&gFdtClientProtocolGuid, NULL,
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(VOID **)&FdtClient);
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ASSERT_EFI_ERROR (Status);
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Status = FdtClient->FindCompatibleNode (FdtClient, "pci-host-ecam-generic",
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&Node);
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if (EFI_ERROR (Status)) {
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DEBUG ((EFI_D_INFO,
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"%a: No 'pci-host-ecam-generic' compatible DT node found\n",
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__FUNCTION__));
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return EFI_NOT_FOUND;
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}
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DEBUG_CODE (
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INT32 Tmp;
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//
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// A DT can legally describe multiple PCI host bridges, but we are not
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// equipped to deal with that. So assert that there is only one.
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//
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Status = FdtClient->FindNextCompatibleNode (FdtClient,
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"pci-host-ecam-generic", Node, &Tmp);
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ASSERT (Status == EFI_NOT_FOUND);
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);
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Status = FdtClient->GetNodeProperty (FdtClient, Node, "reg", &Prop, &Len);
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if (EFI_ERROR (Status) || Len != 2 * sizeof (UINT64)) {
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DEBUG ((EFI_D_ERROR, "%a: 'reg' property not found or invalid\n",
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__FUNCTION__));
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return EFI_PROTOCOL_ERROR;
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}
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//
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// Fetch the ECAM window.
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//
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ConfigBase = SwapBytes64 (((CONST UINT64 *)Prop)[0]);
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ConfigSize = SwapBytes64 (((CONST UINT64 *)Prop)[1]);
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//
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// Fetch the bus range (note: inclusive).
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//
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Status = FdtClient->GetNodeProperty (FdtClient, Node, "bus-range", &Prop,
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&Len);
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if (EFI_ERROR (Status) || Len != 2 * sizeof (UINT32)) {
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DEBUG ((EFI_D_ERROR, "%a: 'bus-range' not found or invalid\n",
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__FUNCTION__));
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return EFI_PROTOCOL_ERROR;
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}
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*BusMin = SwapBytes32 (((CONST UINT32 *)Prop)[0]);
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*BusMax = SwapBytes32 (((CONST UINT32 *)Prop)[1]);
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//
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// Sanity check: the config space must accommodate all 4K register bytes of
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// all 8 functions of all 32 devices of all buses.
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//
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if (*BusMax < *BusMin || *BusMax - *BusMin == MAX_UINT32 ||
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DivU64x32 (ConfigSize, SIZE_4KB * 8 * 32) < *BusMax - *BusMin + 1) {
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DEBUG ((EFI_D_ERROR, "%a: invalid 'bus-range' and/or 'reg'\n",
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__FUNCTION__));
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return EFI_PROTOCOL_ERROR;
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}
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//
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// Iterate over "ranges".
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//
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Status = FdtClient->GetNodeProperty (FdtClient, Node, "ranges", &Prop, &Len);
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if (EFI_ERROR (Status) || Len == 0 ||
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Len % sizeof (DTB_PCI_HOST_RANGE_RECORD) != 0) {
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DEBUG ((EFI_D_ERROR, "%a: 'ranges' not found or invalid\n", __FUNCTION__));
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return EFI_PROTOCOL_ERROR;
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}
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for (RecordIdx = 0; RecordIdx < Len / sizeof (DTB_PCI_HOST_RANGE_RECORD);
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++RecordIdx) {
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CONST DTB_PCI_HOST_RANGE_RECORD *Record;
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Record = (CONST DTB_PCI_HOST_RANGE_RECORD *)Prop + RecordIdx;
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switch (SwapBytes32 (Record->Type) & DTB_PCI_HOST_RANGE_TYPEMASK) {
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case DTB_PCI_HOST_RANGE_IO:
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*IoBase = SwapBytes64 (Record->ChildBase);
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*IoSize = SwapBytes64 (Record->Size);
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IoTranslation = SwapBytes64 (Record->CpuBase) - *IoBase;
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ASSERT (PcdGet64 (PcdPciIoTranslation) == IoTranslation);
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break;
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case DTB_PCI_HOST_RANGE_MMIO32:
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*Mmio32Base = SwapBytes64 (Record->ChildBase);
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*Mmio32Size = SwapBytes64 (Record->Size);
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Mmio32Translation = SwapBytes64 (Record->CpuBase) - *Mmio32Base;
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if (*Mmio32Base > MAX_UINT32 || *Mmio32Size > MAX_UINT32 ||
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*Mmio32Base + *Mmio32Size > SIZE_4GB) {
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DEBUG ((EFI_D_ERROR, "%a: MMIO32 space invalid\n", __FUNCTION__));
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return EFI_PROTOCOL_ERROR;
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}
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ASSERT (PcdGet64 (PcdPciMmio32Translation) == Mmio32Translation);
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if (Mmio32Translation != 0) {
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DEBUG ((EFI_D_ERROR, "%a: unsupported nonzero MMIO32 translation "
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"0x%Lx\n", __FUNCTION__, Mmio32Translation));
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return EFI_UNSUPPORTED;
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}
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break;
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case DTB_PCI_HOST_RANGE_MMIO64:
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*Mmio64Base = SwapBytes64 (Record->ChildBase);
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*Mmio64Size = SwapBytes64 (Record->Size);
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Mmio64Translation = SwapBytes64 (Record->CpuBase) - *Mmio64Base;
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ASSERT (PcdGet64 (PcdPciMmio64Translation) == Mmio64Translation);
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if (Mmio64Translation != 0) {
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DEBUG ((EFI_D_ERROR, "%a: unsupported nonzero MMIO64 translation "
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"0x%Lx\n", __FUNCTION__, Mmio64Translation));
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return EFI_UNSUPPORTED;
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}
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break;
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}
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}
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if (*IoSize == 0 || *Mmio32Size == 0) {
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DEBUG ((EFI_D_ERROR, "%a: %a space empty\n", __FUNCTION__,
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(*IoSize == 0) ? "IO" : "MMIO32"));
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return EFI_PROTOCOL_ERROR;
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}
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//
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// The dynamic PCD PcdPciExpressBaseAddress should have already been set,
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// and should match the value we found in the DT node.
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//
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ASSERT (PcdGet64 (PcdPciExpressBaseAddress) == ConfigBase);
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DEBUG ((EFI_D_INFO, "%a: Config[0x%Lx+0x%Lx) Bus[0x%x..0x%x] "
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"Io[0x%Lx+0x%Lx)@0x%Lx Mem32[0x%Lx+0x%Lx)@0x0 Mem64[0x%Lx+0x%Lx)@0x0\n",
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__FUNCTION__, ConfigBase, ConfigSize, *BusMin, *BusMax, *IoBase, *IoSize,
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IoTranslation, *Mmio32Base, *Mmio32Size, *Mmio64Base, *Mmio64Size));
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// Map the ECAM space in the GCD memory map
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Status = MapGcdMmioSpace (ConfigBase, ConfigSize);
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ASSERT_EFI_ERROR (Status);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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//
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// Map the MMIO window that provides I/O access - the PCI host bridge code
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// is not aware of this translation and so it will only map the I/O view
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// in the GCD I/O map.
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//
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Status = MapGcdMmioSpace (*IoBase + IoTranslation, *IoSize);
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ASSERT_EFI_ERROR (Status);
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return Status;
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}
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STATIC PCI_ROOT_BRIDGE mRootBridge;
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/**
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Return all the root bridge instances in an array.
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@param Count Return the count of root bridge instances.
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@return All the root bridge instances in an array.
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The array should be passed into PciHostBridgeFreeRootBridges()
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when it's not used.
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**/
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PCI_ROOT_BRIDGE *
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EFIAPI
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PciHostBridgeGetRootBridges (
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UINTN *Count
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)
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{
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UINT64 IoBase, IoSize;
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UINT64 Mmio32Base, Mmio32Size;
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UINT64 Mmio64Base, Mmio64Size;
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UINT32 BusMin, BusMax;
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EFI_STATUS Status;
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if (PcdGet64 (PcdPciExpressBaseAddress) == 0) {
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DEBUG ((EFI_D_INFO, "%a: PCI host bridge not present\n", __FUNCTION__));
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*Count = 0;
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return NULL;
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}
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Status = ProcessPciHost (&IoBase, &IoSize, &Mmio32Base, &Mmio32Size,
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&Mmio64Base, &Mmio64Size, &BusMin, &BusMax);
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if (EFI_ERROR (Status)) {
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DEBUG ((EFI_D_ERROR, "%a: failed to discover PCI host bridge: %r\n",
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__FUNCTION__, Status));
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*Count = 0;
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return NULL;
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}
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*Count = 1;
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mRootBridge.Segment = 0;
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mRootBridge.Supports = EFI_PCI_ATTRIBUTE_ISA_IO_16 |
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EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |
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EFI_PCI_ATTRIBUTE_VGA_IO_16 |
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EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
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mRootBridge.Attributes = mRootBridge.Supports;
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mRootBridge.DmaAbove4G = TRUE;
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mRootBridge.NoExtendedConfigSpace = FALSE;
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mRootBridge.ResourceAssigned = FALSE;
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mRootBridge.AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM;
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mRootBridge.Bus.Base = BusMin;
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mRootBridge.Bus.Limit = BusMax;
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mRootBridge.Io.Base = IoBase;
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mRootBridge.Io.Limit = IoBase + IoSize - 1;
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mRootBridge.Mem.Base = Mmio32Base;
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mRootBridge.Mem.Limit = Mmio32Base + Mmio32Size - 1;
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if (sizeof (UINTN) == sizeof (UINT64)) {
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mRootBridge.MemAbove4G.Base = Mmio64Base;
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mRootBridge.MemAbove4G.Limit = Mmio64Base + Mmio64Size - 1;
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if (Mmio64Size > 0) {
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mRootBridge.AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE;
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}
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} else {
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//
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// UEFI mandates a 1:1 virtual-to-physical mapping, so on a 32-bit
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// architecture such as ARM, we will not be able to access 64-bit MMIO
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// BARs unless they are allocated below 4 GB. So ignore the range above
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// 4 GB in this case.
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//
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mRootBridge.MemAbove4G.Base = MAX_UINT64;
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mRootBridge.MemAbove4G.Limit = 0;
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}
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//
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// No separate ranges for prefetchable and non-prefetchable BARs
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//
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mRootBridge.PMem.Base = MAX_UINT64;
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mRootBridge.PMem.Limit = 0;
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mRootBridge.PMemAbove4G.Base = MAX_UINT64;
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mRootBridge.PMemAbove4G.Limit = 0;
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mRootBridge.DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath;
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return &mRootBridge;
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}
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/**
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Free the root bridge instances array returned from
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PciHostBridgeGetRootBridges().
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@param Bridges The root bridge instances array.
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@param Count The count of the array.
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**/
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VOID
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EFIAPI
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PciHostBridgeFreeRootBridges (
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PCI_ROOT_BRIDGE *Bridges,
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UINTN Count
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)
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{
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ASSERT (Count == 1);
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}
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/**
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Inform the platform that the resource conflict happens.
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@param HostBridgeHandle Handle of the Host Bridge.
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@param Configuration Pointer to PCI I/O and PCI memory resource
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descriptors. The Configuration contains the resources
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for all the root bridges. The resource for each root
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bridge is terminated with END descriptor and an
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additional END is appended indicating the end of the
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entire resources. The resource descriptor field
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values follow the description in
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EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
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.SubmitResources().
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**/
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VOID
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EFIAPI
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PciHostBridgeResourceConflict (
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EFI_HANDLE HostBridgeHandle,
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VOID *Configuration
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)
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{
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EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
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UINTN RootBridgeIndex;
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DEBUG ((EFI_D_ERROR, "PciHostBridge: Resource conflict happens!\n"));
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RootBridgeIndex = 0;
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Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
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while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
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DEBUG ((EFI_D_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
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for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
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ASSERT (Descriptor->ResType <
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(sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr) /
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sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr[0])
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)
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);
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DEBUG ((EFI_D_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
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mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
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Descriptor->AddrLen, Descriptor->AddrRangeMax
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));
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if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
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DEBUG ((EFI_D_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n",
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Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
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((Descriptor->SpecificFlag &
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EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
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) != 0) ? L" (Prefetchable)" : L""
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));
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}
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}
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//
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// Skip the END descriptor for root bridge
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//
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ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
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Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
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(EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
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);
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}
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}
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