mirror of https://github.com/acidanthera/audk.git
401 lines
24 KiB
C
401 lines
24 KiB
C
/** @file
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*
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* Copyright (c) 2012-2014, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#ifndef __LAN9118_DXE_HW_H__
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#define __LAN9118_DXE_HW_H__
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/*------------------------------------------------------------------------------
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LAN9118 SMCS Registers
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------------------------------------------------------------------------------*/
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// Base address as on the VE board
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#define LAN9118_BA ((UINT32) PcdGet32(PcdLan9118DxeBaseAddress))
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/* ------------- Tx and Rx Data and Status Memory Locations ------------------*/
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#define LAN9118_RX_DATA (0x00000000 + LAN9118_BA)
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#define LAN9118_RX_STATUS (0x00000040 + LAN9118_BA)
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#define LAN9118_RX_STATUS_PEEK (0x00000044 + LAN9118_BA)
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#define LAN9118_TX_DATA (0x00000020 + LAN9118_BA)
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#define LAN9118_TX_STATUS (0x00000048 + LAN9118_BA)
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#define LAN9118_TX_STATUS_PEEK (0x0000004C + LAN9118_BA)
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/* ------------- System Control and Status Registers -------------------------*/
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#define LAN9118_ID_REV (0x00000050 + LAN9118_BA) // Chip ID and Revision
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#define LAN9118_IRQ_CFG (0x00000054 + LAN9118_BA) // Interrupt Configuration
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#define LAN9118_INT_STS (0x00000058 + LAN9118_BA) // Interrupt Status
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#define LAN9118_INT_EN (0x0000005C + LAN9118_BA) // Interrupt Enable
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//#define LAN9118_RESERVED (0x00000060)
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#define LAN9118_BYTE_TEST (0x00000064 + LAN9118_BA) // Byte Order Test
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#define LAN9118_FIFO_INT (0x00000068 + LAN9118_BA) // FIFO Level Interrupts
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#define LAN9118_RX_CFG (0x0000006C + LAN9118_BA) // Receive Configuration
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#define LAN9118_TX_CFG (0x00000070 + LAN9118_BA) // Transmit Configuration
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#define LAN9118_HW_CFG (0x00000074 + LAN9118_BA) // Hardware Configuration
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#define LAN9118_RX_DP_CTL (0x00000078 + LAN9118_BA) // Receive Data-Path Configuration
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#define LAN9118_RX_FIFO_INF (0x0000007C + LAN9118_BA) // Receive FIFO Information
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#define LAN9118_TX_FIFO_INF (0x00000080 + LAN9118_BA) // Transmit FIFO Information
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#define LAN9118_PMT_CTRL (0x00000084 + LAN9118_BA) // Power Management Control
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#define LAN9118_GPIO_CFG (0x00000088 + LAN9118_BA) // General Purpose IO Configuration
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#define LAN9118_GPT_CFG (0x0000008C + LAN9118_BA) // General Purpose Timer Configuration
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#define LAN9118_GPT_CNT (0x00000090 + LAN9118_BA) // General Purpose Timer Current Count
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#define LAN9118_WORD_SWAP (0x00000098 + LAN9118_BA) // Word Swap Control
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#define LAN9118_FREE_RUN (0x0000009C + LAN9118_BA) // Free-Run 25MHz Counter
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#define LAN9118_RX_DROP (0x000000A0 + LAN9118_BA) // Receiver Dropped Frames Counter
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#define LAN9118_MAC_CSR_CMD (0x000000A4 + LAN9118_BA) // MAC CSR Synchronizer Command
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#define LAN9118_MAC_CSR_DATA (0x000000A8 + LAN9118_BA) // MAC CSR Synchronizer Data
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#define LAN9118_AFC_CFG (0x000000AC + LAN9118_BA) // Automatic Flow Control Configuration
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#define LAN9118_E2P_CMD (0x000000B0 + LAN9118_BA) // EEPROM Command
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#define LAN9118_E2P_DATA (0x000000B4 + LAN9118_BA) // EEPROM Data
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/*
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* Required delays following write cycles (number of BYTE_TEST reads)
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* Taken from Table 6.1 in Revision 1.5 (07-11-08) of the LAN9118 datasheet.
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* Where no delay listed, 0 has been assumed.
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*/
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#define LAN9118_RX_DATA_WR_DELAY 0
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#define LAN9118_RX_STATUS_WR_DELAY 0
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#define LAN9118_RX_STATUS_PEEK_WR_DELAY 0
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#define LAN9118_TX_DATA_WR_DELAY 0
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#define LAN9118_TX_STATUS_WR_DELAY 0
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#define LAN9118_TX_STATUS_PEEK_WR_DELAY 0
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#define LAN9118_ID_REV_WR_DELAY 0
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#define LAN9118_IRQ_CFG_WR_DELAY 3
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#define LAN9118_INT_STS_WR_DELAY 2
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#define LAN9118_INT_EN_WR_DELAY 1
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#define LAN9118_BYTE_TEST_WR_DELAY 0
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#define LAN9118_FIFO_INT_WR_DELAY 1
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#define LAN9118_RX_CFG_WR_DELAY 1
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#define LAN9118_TX_CFG_WR_DELAY 1
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#define LAN9118_HW_CFG_WR_DELAY 1
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#define LAN9118_RX_DP_CTL_WR_DELAY 1
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#define LAN9118_RX_FIFO_INF_WR_DELAY 0
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#define LAN9118_TX_FIFO_INF_WR_DELAY 3
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#define LAN9118_PMT_CTRL_WR_DELAY 7
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#define LAN9118_GPIO_CFG_WR_DELAY 1
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#define LAN9118_GPT_CFG_WR_DELAY 1
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#define LAN9118_GPT_CNT_WR_DELAY 3
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#define LAN9118_WORD_SWAP_WR_DELAY 1
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#define LAN9118_FREE_RUN_WR_DELAY 4
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#define LAN9118_RX_DROP_WR_DELAY 0
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#define LAN9118_MAC_CSR_CMD_WR_DELAY 1
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#define LAN9118_MAC_CSR_DATA_WR_DELAY 1
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#define LAN9118_AFC_CFG_WR_DELAY 1
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#define LAN9118_E2P_CMD_WR_DELAY 1
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#define LAN9118_E2P_DATA_WR_DELAY 1
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/*
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* Required delays following read cycles (number of BYTE_TEST reads)
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* Taken from Table 6.2 in Revision 1.5 (07-11-08) of the LAN9118 datasheet.
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* Where no delay listed, 0 has been assumed.
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*/
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#define LAN9118_RX_DATA_RD_DELAY 3
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#define LAN9118_RX_STATUS_RD_DELAY 3
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#define LAN9118_RX_STATUS_PEEK_RD_DELAY 0
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#define LAN9118_TX_DATA_RD_DELAY 0
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#define LAN9118_TX_STATUS_RD_DELAY 3
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#define LAN9118_TX_STATUS_PEEK_RD_DELAY 0
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#define LAN9118_ID_REV_RD_DELAY 0
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#define LAN9118_IRQ_CFG_RD_DELAY 0
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#define LAN9118_INT_STS_RD_DELAY 0
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#define LAN9118_INT_EN_RD_DELAY 0
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#define LAN9118_BYTE_TEST_RD_DELAY 0
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#define LAN9118_FIFO_INT_RD_DELAY 0
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#define LAN9118_RX_CFG_RD_DELAY 0
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#define LAN9118_TX_CFG_RD_DELAY 0
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#define LAN9118_HW_CFG_RD_DELAY 0
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#define LAN9118_RX_DP_CTL_RD_DELAY 0
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#define LAN9118_RX_FIFO_INF_RD_DELAY 0
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#define LAN9118_TX_FIFO_INF_RD_DELAY 0
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#define LAN9118_PMT_CTRL_RD_DELAY 0
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#define LAN9118_GPIO_CFG_RD_DELAY 0
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#define LAN9118_GPT_CFG_RD_DELAY 0
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#define LAN9118_GPT_CNT_RD_DELAY 0
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#define LAN9118_WORD_SWAP_RD_DELAY 0
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#define LAN9118_FREE_RUN_RD_DELAY 0
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#define LAN9118_RX_DROP_RD_DELAY 4
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#define LAN9118_MAC_CSR_CMD_RD_DELAY 0
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#define LAN9118_MAC_CSR_DATA_RD_DELAY 0
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#define LAN9118_AFC_CFG_RD_DELAY 0
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#define LAN9118_E2P_CMD_RD_DELAY 0
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#define LAN9118_E2P_DATA_RD_DELAY 0
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// Receiver Status bits
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#define RXSTATUS_CRC_ERROR BIT1 // Cyclic Redundancy Check Error
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#define RXSTATUS_DB BIT2 // Dribbling bit: Frame had non-integer multiple of 8bits
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#define RXSTATUS_MII_ERROR BIT3 // Receive error during interception
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#define RXSTATUS_RXW_TO BIT4 // Incomming frame larger than 2kb
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#define RXSTATUS_FT BIT5 // 1: Ether type / 0: 802.3 type frame
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#define RXSTATUS_LCOLL BIT6 // Late collision detected
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#define RXSTATUS_FTL BIT7 // Frame longer than Ether type
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#define RXSTATUS_MCF BIT10 // Frame has Multicast Address
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#define RXSTATUS_RUNT BIT11 // Bad frame
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#define RXSTATUS_LE BIT12 // Actual length of frame different than it claims
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#define RXSTATUS_BCF BIT13 // Frame has Broadcast Address
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#define RXSTATUS_ES BIT15 // Reports any error from bits 1,6,7 and 11
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#define RXSTATUS_PL_MASK (0x3FFF0000) // Packet length bit mask
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#define GET_RXSTATUS_PACKET_LENGTH(RxStatus) (((RxStatus) >> 16) & 0x3FFF) // Packet length bit mask
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#define RXSTATUS_FILT_FAIL BIT30 // The frame failed filtering test
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// Transmitter Status bits
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#define TXSTATUS_DEF BIT0 // Packet tx was deferred
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#define TXSTATUS_EDEF BIT2 // Tx ended because of excessive deferral (> 24288 bit times)
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#define TXSTATUS_CC_MASK (0x00000078) // Collision Count (before Tx) bit mask
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#define TXSTATUS_ECOLL BIT8 // Tx ended because of Excessive Collisions (makes CC_MASK invalid after 16 collisions)
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#define TXSTATUS_LCOLL BIT9 // Packet Tx aborted after coll window of 64 bytes
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#define TXSTATUS_NO_CA BIT10 // Carrier signal not present during Tx (bad?)
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#define TXSTATUS_LOST_CA BIT11 // Lost carrier during Tx
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#define TXSTATUS_ES BIT15 // Reports any errors from bits 1,2,8,9,10 and 11
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#define TXSTATUS_PTAG_MASK (0xFFFF0000) // Mask for Unique ID of packets (So we know who the packets are for)
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// ID_REV register bits
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#define IDREV_ID ((Lan9118MmioRead32(LAN9118_ID_REV) & 0xFFFF0000) >> 16)
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#define IDREV_REV (Lan9118MmioRead32(LAN9118_ID_REV) & 0x0000FFFF)
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// Interrupt Config Register bits
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#define IRQCFG_IRQ_TYPE BIT0 // IRQ Buffer type
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#define IRQCFG_IRQ_POL BIT4 // IRQ Polarity
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#define IRQCFG_IRQ_EN BIT8 // Enable external interrupt
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#define IRQCFG_IRQ_INT BIT12 // State of internal interrupts line
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#define IRQCFG_INT_DEAS_STS BIT13 // State of deassertion interval
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#define IRQCFG_INT_DEAS_CLR BIT14 // Clear the deassertion counter
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#define IRQCFG_INT_DEAS_MASK (0xFF000000) // Interrupt deassertion interval value mask
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// Interrupt Status Register bits
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#define INSTS_GPIO_MASK (0x7) // GPIO interrupts mask
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#define INSTS_RSFL (0x8) // Rx Status FIFO Level reached
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#define INSTS_RSFF BIT4 // Rx Status FIFO full
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#define INSTS_RXDF_INT BIT6 // Rx Frame dropped
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#define INSTS_TSFL BIT7 // Tx Status FIFO Level reached
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#define INSTS_TSFF BIT8 // Tx Status FIFO full
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#define INSTS_TDFA BIT9 // Tx Data FIFO Level exceeded
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#define INSTS_TDFO BIT10 // Tx Data FIFO full
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#define INSTS_TXE BIT13 // Transmitter Error
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#define INSTS_RXE BIT14 // Receiver Error
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#define INSTS_RWT BIT15 // Packet > 2048 bytes received
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#define INSTS_TXSO BIT16 // Tx Status FIFO Overflow
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#define INSTS_PME_INT BIT17 // PME Signal detected
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#define INSTS_PHY_INT BIT18 // Indicates PHY Interrupt
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#define INSTS_GPT_INT BIT19 // GP Timer wrapped past 0xFFFF
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#define INSTS_RXD_INT BIT20 // Indicates that amount of data written to RX_CFG was cleared
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#define INSTS_TX_IOC BIT21 // Finished loading IOC flagged buffer to Tx FIFO
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#define INSTS_RXDFH_INT BIT23 // Rx Dropped frames went past 0x7FFFFFFF
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#define INSTS_RXSTOP_INT BIT24 // Rx was stopped
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#define INSTS_TXSTOP_INT BIT25 // Tx was stopped
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#define INSTS_SW_INT BIT31 // Software Interrupt occurred
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// Interrupt Enable Register bits
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// Hardware Config Register bits
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#define HWCFG_SRST BIT0 // Software Reset bit (SC)
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#define HWCFG_SRST_TO BIT1 // Software Reset Timeout bit (RO)
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#define HWCFG_BMODE BIT2 // 32/16 bit Mode bit (RO)
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#define HWCFG_TX_FIFO_SIZE_MASK (~ (UINT32)0xF0000) // Mask to Clear FIFO Size
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#define HWCFG_MBO BIT20 // Must Be One bit
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// Power Management Control Register
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#define MPTCTRL_READY BIT0 // Device ready indicator
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#define MPTCTRL_PME_EN BIT1 // Enable external PME signals
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#define MPTCTRL_PME_POL BIT2 // Set polarity of PME signals
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#define MPTCTRL_PME_IND BIT3 // Signal type of PME (refer to Spec)
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#define MPTCTRL_WUPS_MASK (0x18) // Wake up status indicator mask
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#define MPTCTRL_PME_TYPE BIT6 // PME Buffer type (Open Drain or Push-Pull)
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#define MPTCTRL_ED_EN BIT8 // Energy-detect enable
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#define MPTCTRL_WOL_EN BIT9 // Enable wake-on-lan
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#define MPTCTRL_PHY_RST BIT10 // Reset the PHY
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#define MPTCTRL_PM_MODE_MASK (BIT12 | BIT13) // Set the power mode
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// PHY control register bits
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#define PHYCR_COLL_TEST BIT7 // Collision test enable
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#define PHYCR_DUPLEX_MODE BIT8 // Set Duplex Mode
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#define PHYCR_RST_AUTO BIT9 // Restart Auto-Negotiation of Link abilities
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#define PHYCR_PD BIT11 // Power-Down switch
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#define PHYCR_AUTO_EN BIT12 // Auto-Negotiation Enable
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#define PHYCR_SPEED_SEL BIT13 // Link Speed Selection
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#define PHYCR_LOOPBK BIT14 // Set loopback mode
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#define PHYCR_RESET BIT15 // Do a PHY reset
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// PHY status register bits
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#define PHYSTS_EXT_CAP BIT0 // Extended Capabilities Register capability
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#define PHYSTS_JABBER BIT1 // Jabber condition detected
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#define PHYSTS_LINK_STS BIT2 // Link Status
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#define PHYSTS_AUTO_CAP BIT3 // Auto-Negotiation Capability
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#define PHYSTS_REMOTE_FAULT BIT4 // Remote fault detected
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#define PHYSTS_AUTO_COMP BIT5 // Auto-Negotiation Completed
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#define PHYSTS_10BASET_HDPLX BIT11 // 10Mbps Half-Duplex ability
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#define PHYSTS_10BASET_FDPLX BIT12 // 10Mbps Full-Duplex ability
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#define PHYSTS_100BASETX_HDPLX BIT13 // 100Mbps Half-Duplex ability
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#define PHYSTS_100BASETX_FDPLX BIT14 // 100Mbps Full-Duplex ability
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#define PHYSTS_100BASE_T4 BIT15 // Base T4 ability
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// PHY Auto-Negotiation advertisement
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#define PHYANA_SEL_MASK ((UINT32)0x1F) // Link type selector
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#define PHYANA_10BASET BIT5 // Advertise 10BASET capability
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#define PHYANA_10BASETFD BIT6 // Advertise 10BASET Full duplex capability
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#define PHYANA_100BASETX BIT7 // Advertise 100BASETX capability
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#define PHYANA_100BASETXFD BIT8 // Advertise 100 BASETX Full duplex capability
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#define PHYANA_PAUSE_OP_MASK (3 << 10) // Advertise PAUSE frame capability
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#define PHYANA_REMOTE_FAULT BIT13 // Remote fault detected
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// PHY Auto-Negotiation Link Partner Ability
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// PHY Auto-Negotiation Expansion
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// PHY Mode control/status
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// PHY Special Modes
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// PHY Special control/status
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// PHY Interrupt Source Flags
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// PHY Interrupt Mask
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// PHY Super Special control/status
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#define PHYSSCS_HCDSPEED_MASK (7 << 2) // Speed indication
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#define PHYSSCS_AUTODONE BIT12 // Auto-Negotiation Done
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// MAC control register bits
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#define MACCR_RX_EN BIT2 // Enable Receiver bit
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#define MACCR_TX_EN BIT3 // Enable Transmitter bit
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#define MACCR_DFCHK BIT5 // Deferral Check bit
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#define MACCR_PADSTR BIT8 // Automatic Pad Stripping bit
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#define MACCR_BOLMT_MASK (0xC0) // Back-Off limit mask
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#define MACCR_DISRTY BIT10 // Disable Transmit Retry bit
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#define MACCR_BCAST BIT11 // Disable Broadcast Frames bit
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#define MACCR_LCOLL BIT12 // Late Collision Control bit
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#define MACCR_HPFILT BIT13 // Hash/Perfect Filtering Mode bit
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#define MACCR_HO BIT15 // Hash Only Filtering Mode
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#define MACCR_PASSBAD BIT16 // Receive all frames that passed filter bit
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#define MACCR_INVFILT BIT17 // Enable Inverse Filtering bit
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#define MACCR_PRMS BIT18 // Promiscuous Mode bit
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#define MACCR_MCPAS BIT19 // Pass all Multicast packets bit
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#define MACCR_FDPX BIT20 // Full Duplex Mode bit
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#define MACCR_LOOPBK BIT21 // Loopback operation mode bit
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#define MACCR_RCVOWN BIT23 // Disable Receive Own frames bit
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#define MACCR_RX_ALL BIT31 // Receive all Packets and route to Filter
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// Wake-Up Control and Status Register
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#define WUCSR_MPEN BIT1 // Magic Packet enable (allow wake from Magic P)
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#define WUCSR_WUEN BIT2 // Allow remote wake up using Wake-Up Frames
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#define WUCSR_MPR_MASK (0x10) // Received Magic Packet
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#define WUCSR_WUFR_MASK (0x20) // Received Wake-Up Frame
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#define WUCSR_GUE BIT9 // Enable wake on global unicast frames
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// RX Configuration Register bits
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#define RXCFG_RXDOFF_MASK (0x1F00) // Rx Data Offset in Bytes
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#define RXCFG_RX_DUMP BIT15 // Clear Rx data and status FIFOs
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#define RXCFG_RX_DMA_CNT_MASK (0x0FFF0000) // Amount of data to be read from Rx FIFO
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#define RXCFG_RX_DMA_CNT(cnt) (((cnt) & 0xFFF) << 16) // Amount of data to be read from Rx FIFO
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#define RXCFG_RX_END_ALIGN_MASK (0xC0000000) // Alignment to preserve
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// TX Configuration Register bits
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#define TXCFG_STOP_TX BIT0 // Stop the transmitter
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#define TXCFG_TX_ON BIT1 // Start the transmitter
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#define TXCFG_TXSAO BIT2 // Tx Status FIFO full
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#define TXCFG_TXD_DUMP BIT14 // Clear Tx Data FIFO
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#define TXCFG_TXS_DUMP BIT15 // Clear Tx Status FIFO
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// Rx FIFO Information Register bits
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#define RXFIFOINF_RXDUSED_MASK (0xFFFF) // Rx Data FIFO Used Space
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#define RXFIFOINF_RXSUSED_MASK (0xFF0000) // Rx Status FIFO Used Space
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// Tx FIFO Information Register bits
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#define TXFIFOINF_TDFREE_MASK (0xFFFF) // Tx Data FIFO Free Space
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#define TXFIFOINF_TXSUSED_MASK (0xFF0000) // Tx Status FIFO Used Space
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// E2P Register
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#define E2P_EPC_BUSY BIT31
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#define E2P_EPC_CMD_READ (0)
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#define E2P_EPC_TIMEOUT BIT9
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#define E2P_EPC_MAC_ADDRESS_LOADED BIT8
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#define E2P_EPC_ADDRESS(address) ((address) & 0xFFFF)
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// GPIO Configuration register
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#define GPIO_GPIO0_PUSH_PULL BIT16
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#define GPIO_GPIO1_PUSH_PULL BIT17
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#define GPIO_GPIO2_PUSH_PULL BIT18
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#define GPIO_LED1_ENABLE BIT28
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#define GPIO_LED2_ENABLE BIT29
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#define GPIO_LED3_ENABLE BIT30
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// MII_ACC bits
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#define MII_ACC_MII_BUSY BIT0
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#define MII_ACC_MII_WRITE BIT1
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#define MII_ACC_MII_READ 0
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#define MII_ACC_PHY_VALUE BIT11
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#define MII_ACC_MII_REG_INDEX(index) (((index) & 0x1F) << 6)
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//
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// PHY Control Indexes
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//
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#define PHY_INDEX_BASIC_CTRL 0
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#define PHY_INDEX_BASIC_STATUS 1
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#define PHY_INDEX_ID1 2
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#define PHY_INDEX_ID2 3
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#define PHY_INDEX_AUTO_NEG_ADVERT 4
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#define PHY_INDEX_AUTO_NEG_LINK_ABILITY 5
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#define PHY_INDEX_AUTO_NEG_EXP 6
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#define PHY_INDEX_MODE 17
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#define PHY_INDEX_SPECIAL_MODES 18
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#define PHY_INDEX_SPECIAL_CTLR 27
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#define PHY_INDEX_INT_SRC 29
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#define PHY_INDEX_INT_MASK 30
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#define PHY_INDEX_SPECIAL_PHY_CTLR 31
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// Indirect MAC Indexes
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#define INDIRECT_MAC_INDEX_CR 1
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#define INDIRECT_MAC_INDEX_ADDRH 2
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#define INDIRECT_MAC_INDEX_ADDRL 3
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#define INDIRECT_MAC_INDEX_HASHH 4
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#define INDIRECT_MAC_INDEX_HASHL 5
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#define INDIRECT_MAC_INDEX_MII_ACC 6
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#define INDIRECT_MAC_INDEX_MII_DATA 7
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//
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// MAC CSR Synchronizer Command register
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//
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#define MAC_CSR_BUSY BIT31
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#define MAC_CSR_READ BIT30
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#define MAC_CSR_WRITE 0
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#define MAC_CSR_ADDR(Addr) ((Addr) & 0xFF)
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//
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// TX Packet Format
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//
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#define TX_CMD_A_COMPLETION_INT BIT31
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#define TX_CMD_A_FIRST_SEGMENT BIT13
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#define TX_CMD_A_LAST_SEGMENT BIT12
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#define TX_CMD_A_BUFF_SIZE(size) ((size) & 0x000003FF)
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#define TX_CMD_A_DATA_START_OFFSET(offset) (((offset) & 0x1F) << 16)
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#define TX_CMD_B_PACKET_LENGTH(size) ((size) & 0x000003FF)
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#define TX_CMD_B_PACKET_TAG(tag) (((tag) & 0x3FF) << 16)
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// Hardware Configuration Register
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#define HW_CFG_TX_FIFO_SIZE_MASK (0xF << 16)
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#define HW_CFG_TX_FIFO_SIZE(size) (((size) & 0xF) << 16)
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// EEPROM Definition
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#define EEPROM_EXTERNAL_SERIAL_EEPROM 0xA5
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//
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// Conditional compilation flags
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//
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//#define EVAL_PERFORMANCE
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#endif /* __LAN9118_DXE_HDR_H__ */
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