mirror of https://github.com/acidanthera/audk.git
543 lines
13 KiB
C
543 lines
13 KiB
C
/** @file
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HTE handling routines for MRC use.
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Copyright (c) 2013-2015 Intel Corporation.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "mrc.h"
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#include "memory_options.h"
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#include "io.h"
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#include "hte.h"
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#ifdef SIM
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VOID delay_n(UINT32 nanoseconds);
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#define MySimStall(a) delay_n(a/1000)
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#endif
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STATIC VOID EnableAllHteErrors(
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UINT8 Mask)
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/*++
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Routine Description:
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This function enables to HTE to detect all possible errors for
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the given training parameters (per-bit or full byte lane).
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Returns:
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None
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--*/
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{
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isbW32m(HTE, 0x000200A2, 0xFFFFFFFF);
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isbW32m(HTE, 0x000200A3, 0x000000FF);
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isbW32m(HTE, 0x000200A4, 0x00000000);
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}
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STATIC UINT32 CheckHteErrors(
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VOID)
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/*++
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Routine Description:
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This function goes and reads the HTE register in order to find any error
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Returns:
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The errors detected in the HTE status register
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--*/
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{
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return isbR32m(HTE, 0x000200A7);
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}
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STATIC VOID WaitForHteComplete(
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VOID)
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/*++
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Routine Description:
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This function waits until HTE finishes
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Returns:
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None
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--*/
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{
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UINT32 Tmp;
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ENTERFN();
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//
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// Is the test done?
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//
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do
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{
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#ifdef SIM
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MySimStall (35000); // 35 ns delay
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#endif
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} while (0 != (isbR32m(HTE, 0x00020012) & BIT30));
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Tmp = isbR32m(HTE, 0x00020011);
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Tmp = Tmp | BIT9;
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Tmp = Tmp & ~(BIT13 | BIT12);
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isbW32m(HTE, 0x00020011, Tmp);
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LEAVEFN();
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}
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STATIC VOID ClearHteErrorRegisters(
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VOID)
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/*++
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Routine Description:
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Clears registers related with errors in the HTE.
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Returns:
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None
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--*/
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{
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UINT32 Tmp;
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//
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// Clear all HTE errors and enable error checking
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// for burst and chunk.
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//
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Tmp = isbR32m(HTE, 0x000200A1);
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Tmp |= BIT8;
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isbW32m(HTE, 0x000200A1, Tmp);
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}
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UINT32 HteMemInit(
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MRC_PARAMS *CurrentMrcData,
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UINT8 MemInitFlag,
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UINT8 HaltHteEngineOnError)
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/*++
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Routine Description:
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Uses HW HTE engine to initialize or test all memory attached to a given DUNIT.
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If MemInitFlag is 1, this routine writes 0s to all memory locations to initialize
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ECC.
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If MemInitFlag is 0, this routine will send an 5AA55AA5 pattern to all memory
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locations on the RankMask and then read it back. Then it sends an A55AA55A
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pattern to all memory locations on the RankMask and reads it back.
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Arguments:
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CurrentMrcData: Host struture for all MRC global data.
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MemInitFlag: 0 for memtest, 1 for meminit.
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HaltHteEngineOnError: Halt the HTE engine on first error observed, or keep
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running to see how many errors are found.
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Returns:
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Errors register showing HTE failures.
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Also prints out which rank failed the HTE test if failure occurs.
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For rank detection to work, the address map must be left in its default
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state. If MRC changes the address map, this function must be modified
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to change it back to default at the beginning, then restore it at the end.
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--*/
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{
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UINT32 Offset;
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UINT8 TestNum;
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UINT8 i;
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//
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// Clear out the error registers at the start of each memory
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// init or memory test run.
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//
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ClearHteErrorRegisters();
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isbW32m(HTE, 0x00020062, 0x00000015);
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for (Offset = 0x80; Offset <= 0x8F; Offset++)
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{
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isbW32m(HTE, Offset, ((Offset & 1) ? 0xA55A : 0x5AA5));
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}
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isbW32m(HTE, 0x00020021, 0x00000000);
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#ifdef QUICKSIM
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// Just do 4 cache lines for simulation memtest to save time.
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isbW32m(HTE, 0x00020022, 4-1);
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#else
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isbW32m(HTE, 0x00020022, (CurrentMrcData->mem_size >> 6) - 1);
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#endif
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isbW32m(HTE, 0x00020063, 0xAAAAAAAA);
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isbW32m(HTE, 0x00020064, 0xCCCCCCCC);
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isbW32m(HTE, 0x00020065, 0xF0F0F0F0);
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isbW32m(HTE, 0x00020066, 0x03000000);
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switch (MemInitFlag)
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{
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case MrcMemInit:
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TestNum = 1; // Only 1 write pass through memory is needed to initialize ECC.
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break;
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case MrcMemTest:
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TestNum = 4; // Write/read then write/read with inverted pattern.
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break;
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default:
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DPF(D_INFO, "Unknown parameter for MemInitFlag: %d\n", MemInitFlag);
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return 0xFFFFFFFF;
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break;
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}
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DPF(D_INFO, "HteMemInit");
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for (i = 0; i < TestNum; i++)
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{
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DPF(D_INFO, ".");
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if (i == 0)
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{
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isbW32m(HTE, 0x00020061, 0x00000000);
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isbW32m(HTE, 0x00020020, 0x00110010);
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}
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else if (i == 1)
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{
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isbW32m(HTE, 0x00020061, 0x00000000);
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isbW32m(HTE, 0x00020020, 0x00010010);
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}
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else if (i == 2)
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{
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isbW32m(HTE, 0x00020061, 0x00010100);
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isbW32m(HTE, 0x00020020, 0x00110010);
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}
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else
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{
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isbW32m(HTE, 0x00020061, 0x00010100);
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isbW32m(HTE, 0x00020020, 0x00010010);
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}
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isbW32m(HTE, 0x00020011, 0x00111000);
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isbW32m(HTE, 0x00020011, 0x00111100);
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WaitForHteComplete();
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//
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// If this is a READ pass, check for errors at the end.
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//
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if ((i % 2) == 1)
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{
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//
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// Return immediately if error.
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//
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if (CheckHteErrors())
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{
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break;
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}
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}
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}
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DPF(D_INFO, "done\n", i);
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return CheckHteErrors();
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}
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STATIC UINT16 BasicDataCompareHte(
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MRC_PARAMS *CurrentMrcData,
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UINT32 Address,
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UINT8 FirstRun,
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UINT8 Mode)
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/*++
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Routine Description:
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Execute basic single cache line memory write/read/verify test using simple constant
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pattern (different for READ_RAIN and WRITE_TRAIN modes.
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See BasicWriteReadHTE which is external visible wrapper.
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Arguments:
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CurrentMrcData: Host struture for all MRC global data.
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Address: memory adress being tested (must hit specific channel/rank)
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FirstRun: If set then hte registers are configured, otherwise
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it is assumed configuration is done and just re-run the test.
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Mode: READ_TRAIN or WRITE_TRAIN (the difference is in the pattern)
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Returns:
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Returns byte lane failure on each bit (for Quark only bit0 and bit1)
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--*/
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{
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UINT32 Pattern;
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UINT32 Offset;
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if (FirstRun)
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{
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isbW32m(HTE, 0x00020020, 0x01B10021);
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isbW32m(HTE, 0x00020021, 0x06000000);
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isbW32m(HTE, 0x00020022, Address >> 6);
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isbW32m(HTE, 0x00020062, 0x00800015);
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isbW32m(HTE, 0x00020063, 0xAAAAAAAA);
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isbW32m(HTE, 0x00020064, 0xCCCCCCCC);
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isbW32m(HTE, 0x00020065, 0xF0F0F0F0);
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isbW32m(HTE, 0x00020061, 0x00030008);
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if (Mode == WRITE_TRAIN)
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{
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Pattern = 0xC33C0000;
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}
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else // READ_TRAIN
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{
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Pattern = 0xAA5555AA;
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}
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for (Offset = 0x80; Offset <= 0x8F; Offset++)
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{
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isbW32m(HTE, Offset, Pattern);
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}
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}
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isbW32m(HTE, 0x000200A1, 0xFFFF1000);
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isbW32m(HTE, 0x00020011, 0x00011000);
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isbW32m(HTE, 0x00020011, 0x00011100);
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WaitForHteComplete();
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//
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// Return bits 15:8 of HTE_CH0_ERR_XSTAT to check for any bytelane errors.
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//
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return ((CheckHteErrors() >> 8) & 0xFF);
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}
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STATIC UINT16 ReadWriteDataCompareHte(
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MRC_PARAMS *CurrentMrcData,
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UINT32 Address,
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UINT8 LoopCount,
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UINT32 LfsrSeedVictim,
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UINT32 LfsrSeedAggressor,
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UINT8 VictimBit,
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UINT8 FirstRun)
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/*++
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Routine Description:
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Examines single cache line memory with write/read/verify test using
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multiple data patterns (victim-aggressor algorithm).
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See WriteStressBitLanesHTE which is external visible wrapper.
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Arguments:
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CurrentMrcData: host struture for all MRC global data.
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Address: memory adress being tested (must hit specific channel/rank)
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LoopCount: number of test iterations
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LfsrSeedXxx: victim aggressor data pattern seed
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VictimBit: should be 0 as auto rotate feature is in use.
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FirstRun: If set then hte registers are configured, otherwise
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it is assumed configuration is done and just re-run the test.
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Returns:
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Returns byte lane failure on each bit (for Quark only bit0 and bit1)
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--*/
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{
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UINT32 Offset;
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UINT32 Tmp;
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if (FirstRun)
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{
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isbW32m(HTE, 0x00020020, 0x00910024);
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isbW32m(HTE, 0x00020023, 0x00810024);
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isbW32m(HTE, 0x00020021, 0x06070000);
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isbW32m(HTE, 0x00020024, 0x06070000);
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isbW32m(HTE, 0x00020022, Address >> 6);
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isbW32m(HTE, 0x00020025, Address >> 6);
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isbW32m(HTE, 0x00020062, 0x0000002A);
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isbW32m(HTE, 0x00020063, LfsrSeedVictim);
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isbW32m(HTE, 0x00020064, LfsrSeedAggressor);
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isbW32m(HTE, 0x00020065, LfsrSeedVictim);
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//
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// Write the pattern buffers to select the victim bit. Start with bit0.
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//
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for (Offset = 0x80; Offset <= 0x8F; Offset++)
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{
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if ((Offset % 8) == VictimBit)
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{
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isbW32m(HTE, Offset, 0x55555555);
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}
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else
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{
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isbW32m(HTE, Offset, 0xCCCCCCCC);
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}
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}
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isbW32m(HTE, 0x00020061, 0x00000000);
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isbW32m(HTE, 0x00020066, 0x03440000);
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isbW32m(HTE, 0x000200A1, 0xFFFF1000);
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}
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Tmp = 0x10001000 | (LoopCount << 16);
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isbW32m(HTE, 0x00020011, Tmp);
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isbW32m(HTE, 0x00020011, Tmp | BIT8);
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WaitForHteComplete();
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return (CheckHteErrors() >> 8) & 0xFF;
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}
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UINT16 BasicWriteReadHTE(
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MRC_PARAMS *CurrentMrcData,
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UINT32 Address,
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UINT8 FirstRun,
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UINT8 Mode)
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/*++
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Routine Description:
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Execute basic single cache line memory write/read/verify test using simple constant
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pattern (different for READ_RAIN and WRITE_TRAIN modes.
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Arguments:
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CurrentMrcData: Host struture for all MRC global data.
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Address: memory adress being tested (must hit specific channel/rank)
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FirstRun: If set then hte registers are configured, otherwise
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it is assumed configuration is done and just re-run the test.
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Mode: READ_TRAIN or WRITE_TRAIN (the difference is in the pattern)
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Returns:
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Returns byte lane failure on each bit (for Quark only bit0 and bit1)
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--*/
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{
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UINT16 ByteLaneErrors;
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ENTERFN();
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//
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// Enable all error reporting in preparation for HTE test.
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//
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EnableAllHteErrors(0xFF);
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ClearHteErrorRegisters();
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ByteLaneErrors = BasicDataCompareHte(CurrentMrcData, Address, FirstRun,
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Mode);
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LEAVEFN();
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return ByteLaneErrors;
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}
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UINT16 WriteStressBitLanesHTE(
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MRC_PARAMS *CurrentMrcData,
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UINT32 Address,
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UINT8 FirstRun)
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/*++
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Routine Description:
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Examines single cache line memory with write/read/verify test using
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multiple data patterns (victim-aggressor algorithm).
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Arguments:
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CurrentMrcData: host struture for all MRC global data.
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Address: memory adress being tested (must hit specific channel/rank)
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FirstRun: If set then hte registers are configured, otherwise
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it is assumed configuration is done and just re-run the test.
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Returns:
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Returns byte lane failure on each bit (for Quark only bit0 and bit1)
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--*/
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{
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UINT16 ByteLaneErrors;
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UINT8 VictimBit = 0;
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ENTERFN();
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//
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// Enable all error reporting in preparation for HTE test.
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//
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EnableAllHteErrors(0xFF);
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ClearHteErrorRegisters();
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//
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// Loop through each bit in the bytelane. Each pass creates a victim bit
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// while keeping all other bits the same - as aggressors.
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// AVN HTE adds an auto-rotate feature which allows us to program the entire victim/aggressor
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// sequence in 1 step. The victim bit rotates on each pass so no need to have software implement
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// a victim bit loop like on VLV.
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//
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ByteLaneErrors = ReadWriteDataCompareHte(CurrentMrcData, Address,
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HTE_LOOP_CNT, HTE_LFSR_VICTIM_SEED, HTE_LFSR_AGRESSOR_SEED, VictimBit,
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FirstRun);
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LEAVEFN();
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return ByteLaneErrors;
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}
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VOID HteMemOp(
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UINT32 Address,
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UINT8 FirstRun,
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UINT8 IsWrite)
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/*++
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Routine Description:
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Execute basic single cache line memory write or read.
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This is just for receive enable / fine write levelling purpose.
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Arguments:
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CurrentMrcData: Host structure for all MRC global data.
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Address: memory address used (must hit specific channel/rank)
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FirstRun: If set then hte registers are configured, otherwise
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it is assumed configuration is done and just re-run the test.
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IsWrite: When non-zero memory write operation executed, otherwise read
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Returns:
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None
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--*/
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{
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UINT32 Offset;
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UINT32 Tmp;
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EnableAllHteErrors(0xFF);
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ClearHteErrorRegisters();
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if (FirstRun)
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{
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Tmp = IsWrite ? 0x01110021 : 0x01010021;
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isbW32m(HTE, 0x00020020, Tmp);
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isbW32m(HTE, 0x00020021, 0x06000000);
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isbW32m(HTE, 0x00020022, Address >> 6);
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isbW32m(HTE, 0x00020062, 0x00800015);
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isbW32m(HTE, 0x00020063, 0xAAAAAAAA);
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isbW32m(HTE, 0x00020064, 0xCCCCCCCC);
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isbW32m(HTE, 0x00020065, 0xF0F0F0F0);
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isbW32m(HTE, 0x00020061, 0x00030008);
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for (Offset = 0x80; Offset <= 0x8F; Offset++)
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{
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isbW32m(HTE, Offset, 0xC33C0000);
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}
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}
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isbW32m(HTE, 0x000200A1, 0xFFFF1000);
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isbW32m(HTE, 0x00020011, 0x00011000);
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isbW32m(HTE, 0x00020011, 0x00011100);
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WaitForHteComplete();
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}
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