mirror of https://github.com/acidanthera/audk.git
139 lines
3.2 KiB
C
139 lines
3.2 KiB
C
/** @file
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Declaration of IO handling routines.
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Copyright (c) 2013-2015 Intel Corporation.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef __IO_H
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#define __IO_H
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#include "core_types.h"
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#include "general_definitions.h"
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#include "gen5_iosf_sb_definitions.h"
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// Instruction not present on Quark
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#define SFENCE()
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#define DEAD_LOOP() for(;;);
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////
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// Define each of the IOSF_SB ports used by MRC
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//
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//
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// Has to be 0 because of emulation static data
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// initialisation:
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// Space_t EmuSpace[ SPACE_COUNT] = {0};
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//
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#define FREE 0x000
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// Pseudo side-band ports for access abstraction
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// See Wr32/Rd32 functions
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#define MEM 0x101
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#define MMIO 0x102
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#define DCMD 0x0A0
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// Real side-band ports
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// See Wr32/Rd32 functions
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#define MCU 0x001
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#define HOST_BRIDGE 0x003
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#define MEMORY_MANAGER 0x005
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#define HTE 0x011
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#define DDRPHY 0x012
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#define FUSE 0x033
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// End of IOSF_SB ports
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////
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// Pciexbar address
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#define EC_BASE 0xE0000000
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#define PCIADDR(bus,dev,fn,reg) ( \
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(EC_BASE) + \
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((bus) << 20) + \
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((dev) << 15) + \
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((fn) << 12) + \
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(reg))
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// Various offsets used in the building sideband commands.
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#define SB_OPCODE_OFFSET 24
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#define SB_PORT_OFFSET 16
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#define SB_REG_OFFEST 8
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// Sideband opcodes
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#define SB_REG_READ_OPCODE 0x10
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#define SB_REG_WRITE_OPCODE 0x11
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#define SB_FUSE_REG_READ_OPCODE 0x06
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#define SB_FUSE_REG_WRITE_OPCODE 0x07
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#define SB_DDRIO_REG_READ_OPCODE 0x06
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#define SB_DDRIO_REG_WRITE_OPCODE 0x07
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#define SB_DRAM_CMND_OPCODE 0x68
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#define SB_WAKE_CMND_OPCODE 0xCA
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#define SB_SUSPEND_CMND_OPCODE 0xCC
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// Register addresses for sideband command and data.
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#define SB_PACKET_REG 0x00D0
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#define SB_DATA_REG 0x00D4
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#define SB_HADR_REG 0x00D8
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// We always flag all 4 bytes in the register reads/writes as required.
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#define SB_ALL_BYTES_ENABLED 0xF0
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#define SB_COMMAND(Opcode, Port, Reg) \
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((Opcode << SB_OPCODE_OFFSET) | \
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(Port << SB_PORT_OFFSET) | \
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(Reg << SB_REG_OFFEST) | \
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SB_ALL_BYTES_ENABLED)
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// iosf
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#define isbM32m WrMask32
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#define isbW32m Wr32
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#define isbR32m Rd32
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// pci
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void pciwrite32(
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uint32_t bus,
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uint32_t dev,
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uint32_t fn,
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uint32_t reg,
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uint32_t data);
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uint32_t pciread32(
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uint32_t bus,
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uint32_t dev,
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uint32_t fn,
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uint32_t reg);
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// general
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uint32_t Rd32(
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uint32_t unit,
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uint32_t addr);
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void Wr32(
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uint32_t unit,
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uint32_t addr,
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uint32_t data);
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void WrMask32(
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uint32_t unit,
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uint32_t addr,
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uint32_t data,
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uint32_t mask);
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#endif
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