mirror of https://github.com/acidanthera/audk.git
299 lines
17 KiB
C
299 lines
17 KiB
C
/** @file
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Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef __OMAP3530_PAD_CONFIGURATION_H__
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#define __OMAP3530_PAD_CONFIGURATION_H__
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#define SYSTEM_CONTROL_MODULE_BASE 0x48002000
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//Pin definition
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#define SDRC_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x030)
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#define SDRC_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x032)
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#define SDRC_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x034)
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#define SDRC_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x036)
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#define SDRC_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x038)
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#define SDRC_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x03A)
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#define SDRC_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x03C)
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#define SDRC_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x03E)
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#define SDRC_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x040)
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#define SDRC_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x042)
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#define SDRC_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x044)
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#define SDRC_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x046)
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#define SDRC_D12 (SYSTEM_CONTROL_MODULE_BASE + 0x048)
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#define SDRC_D13 (SYSTEM_CONTROL_MODULE_BASE + 0x04A)
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#define SDRC_D14 (SYSTEM_CONTROL_MODULE_BASE + 0x04C)
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#define SDRC_D15 (SYSTEM_CONTROL_MODULE_BASE + 0x04E)
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#define SDRC_D16 (SYSTEM_CONTROL_MODULE_BASE + 0x050)
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#define SDRC_D17 (SYSTEM_CONTROL_MODULE_BASE + 0x052)
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#define SDRC_D18 (SYSTEM_CONTROL_MODULE_BASE + 0x054)
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#define SDRC_D19 (SYSTEM_CONTROL_MODULE_BASE + 0x056)
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#define SDRC_D20 (SYSTEM_CONTROL_MODULE_BASE + 0x058)
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#define SDRC_D21 (SYSTEM_CONTROL_MODULE_BASE + 0x05A)
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#define SDRC_D22 (SYSTEM_CONTROL_MODULE_BASE + 0x05C)
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#define SDRC_D23 (SYSTEM_CONTROL_MODULE_BASE + 0x05E)
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#define SDRC_D24 (SYSTEM_CONTROL_MODULE_BASE + 0x060)
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#define SDRC_D25 (SYSTEM_CONTROL_MODULE_BASE + 0x062)
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#define SDRC_D26 (SYSTEM_CONTROL_MODULE_BASE + 0x064)
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#define SDRC_D27 (SYSTEM_CONTROL_MODULE_BASE + 0x066)
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#define SDRC_D28 (SYSTEM_CONTROL_MODULE_BASE + 0x068)
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#define SDRC_D29 (SYSTEM_CONTROL_MODULE_BASE + 0x06A)
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#define SDRC_D30 (SYSTEM_CONTROL_MODULE_BASE + 0x06C)
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#define SDRC_D31 (SYSTEM_CONTROL_MODULE_BASE + 0x06E)
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#define SDRC_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x070)
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#define SDRC_DQS0 (SYSTEM_CONTROL_MODULE_BASE + 0x072)
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#define SDRC_CKE0 (SYSTEM_CONTROL_MODULE_BASE + 0x262)
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#define SDRC_CKE1 (SYSTEM_CONTROL_MODULE_BASE + 0x264)
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#define SDRC_DQS1 (SYSTEM_CONTROL_MODULE_BASE + 0x074)
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#define SDRC_DQS2 (SYSTEM_CONTROL_MODULE_BASE + 0x076)
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#define SDRC_DQS3 (SYSTEM_CONTROL_MODULE_BASE + 0x078)
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#define GPMC_A1 (SYSTEM_CONTROL_MODULE_BASE + 0x07A)
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#define GPMC_A2 (SYSTEM_CONTROL_MODULE_BASE + 0x07C)
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#define GPMC_A3 (SYSTEM_CONTROL_MODULE_BASE + 0x07E)
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#define GPMC_A4 (SYSTEM_CONTROL_MODULE_BASE + 0x080)
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#define GPMC_A5 (SYSTEM_CONTROL_MODULE_BASE + 0x082)
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#define GPMC_A6 (SYSTEM_CONTROL_MODULE_BASE + 0x084)
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#define GPMC_A7 (SYSTEM_CONTROL_MODULE_BASE + 0x086)
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#define GPMC_A8 (SYSTEM_CONTROL_MODULE_BASE + 0x088)
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#define GPMC_A9 (SYSTEM_CONTROL_MODULE_BASE + 0x08A)
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#define GPMC_A10 (SYSTEM_CONTROL_MODULE_BASE + 0x08C)
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#define GPMC_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x08E)
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#define GPMC_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x090)
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#define GPMC_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x092)
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#define GPMC_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x094)
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#define GPMC_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x096)
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#define GPMC_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x098)
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#define GPMC_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x09A)
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#define GPMC_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x09C)
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#define GPMC_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x09E)
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#define GPMC_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x0A0)
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#define GPMC_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x0A2)
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#define GPMC_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x0A4)
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#define GPMC_D12 (SYSTEM_CONTROL_MODULE_BASE + 0x0A6)
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#define GPMC_D13 (SYSTEM_CONTROL_MODULE_BASE + 0x0A8)
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#define GPMC_D14 (SYSTEM_CONTROL_MODULE_BASE + 0x0AA)
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#define GPMC_D15 (SYSTEM_CONTROL_MODULE_BASE + 0x0AC)
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#define GPMC_NCS0 (SYSTEM_CONTROL_MODULE_BASE + 0x0AE)
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#define GPMC_NCS1 (SYSTEM_CONTROL_MODULE_BASE + 0x0B0)
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#define GPMC_NCS2 (SYSTEM_CONTROL_MODULE_BASE + 0x0B2)
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#define GPMC_NCS3 (SYSTEM_CONTROL_MODULE_BASE + 0x0B4)
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#define GPMC_NCS4 (SYSTEM_CONTROL_MODULE_BASE + 0x0B6)
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#define GPMC_NCS5 (SYSTEM_CONTROL_MODULE_BASE + 0x0B8)
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#define GPMC_NCS6 (SYSTEM_CONTROL_MODULE_BASE + 0x0BA)
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#define GPMC_NCS7 (SYSTEM_CONTROL_MODULE_BASE + 0x0BC)
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#define GPMC_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x0BE)
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#define GPMC_NADV_ALE (SYSTEM_CONTROL_MODULE_BASE + 0x0C0)
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#define GPMC_NOE (SYSTEM_CONTROL_MODULE_BASE + 0x0C2)
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#define GPMC_NWE (SYSTEM_CONTROL_MODULE_BASE + 0x0C4)
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#define GPMC_NBE0_CLE (SYSTEM_CONTROL_MODULE_BASE + 0x0C6)
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#define GPMC_NBE1 (SYSTEM_CONTROL_MODULE_BASE + 0x0C8)
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#define GPMC_NWP (SYSTEM_CONTROL_MODULE_BASE + 0x0CA)
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#define GPMC_WAIT0 (SYSTEM_CONTROL_MODULE_BASE + 0x0CC)
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#define GPMC_WAIT1 (SYSTEM_CONTROL_MODULE_BASE + 0x0CE)
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#define GPMC_WAIT2 (SYSTEM_CONTROL_MODULE_BASE + 0x0D0)
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#define GPMC_WAIT3 (SYSTEM_CONTROL_MODULE_BASE + 0x0D2)
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#define DSS_PCLK (SYSTEM_CONTROL_MODULE_BASE + 0x0D4)
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#define DSS_HSYNC (SYSTEM_CONTROL_MODULE_BASE + 0x0D6)
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#define DSS_PSYNC (SYSTEM_CONTROL_MODULE_BASE + 0x0D8)
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#define DSS_ACBIAS (SYSTEM_CONTROL_MODULE_BASE + 0x0DA)
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#define DSS_DATA0 (SYSTEM_CONTROL_MODULE_BASE + 0x0DC)
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#define DSS_DATA1 (SYSTEM_CONTROL_MODULE_BASE + 0x0DE)
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#define DSS_DATA2 (SYSTEM_CONTROL_MODULE_BASE + 0x0E0)
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#define DSS_DATA3 (SYSTEM_CONTROL_MODULE_BASE + 0x0E2)
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#define DSS_DATA4 (SYSTEM_CONTROL_MODULE_BASE + 0x0E4)
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#define DSS_DATA5 (SYSTEM_CONTROL_MODULE_BASE + 0x0E6)
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#define DSS_DATA6 (SYSTEM_CONTROL_MODULE_BASE + 0x0E8)
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#define DSS_DATA7 (SYSTEM_CONTROL_MODULE_BASE + 0x0EA)
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#define DSS_DATA8 (SYSTEM_CONTROL_MODULE_BASE + 0x0EC)
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#define DSS_DATA9 (SYSTEM_CONTROL_MODULE_BASE + 0x0EE)
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#define DSS_DATA10 (SYSTEM_CONTROL_MODULE_BASE + 0x0F0)
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#define DSS_DATA11 (SYSTEM_CONTROL_MODULE_BASE + 0x0F2)
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#define DSS_DATA12 (SYSTEM_CONTROL_MODULE_BASE + 0x0F4)
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#define DSS_DATA13 (SYSTEM_CONTROL_MODULE_BASE + 0x0F6)
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#define DSS_DATA14 (SYSTEM_CONTROL_MODULE_BASE + 0x0F8)
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#define DSS_DATA15 (SYSTEM_CONTROL_MODULE_BASE + 0x0FA)
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#define DSS_DATA16 (SYSTEM_CONTROL_MODULE_BASE + 0x0FC)
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#define DSS_DATA17 (SYSTEM_CONTROL_MODULE_BASE + 0x0FE)
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#define DSS_DATA18 (SYSTEM_CONTROL_MODULE_BASE + 0x100)
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#define DSS_DATA19 (SYSTEM_CONTROL_MODULE_BASE + 0x102)
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#define DSS_DATA20 (SYSTEM_CONTROL_MODULE_BASE + 0x104)
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#define DSS_DATA21 (SYSTEM_CONTROL_MODULE_BASE + 0x106)
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#define DSS_DATA22 (SYSTEM_CONTROL_MODULE_BASE + 0x108)
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#define DSS_DATA23 (SYSTEM_CONTROL_MODULE_BASE + 0x10A)
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#define CAM_HS (SYSTEM_CONTROL_MODULE_BASE + 0x10C)
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#define CAM_VS (SYSTEM_CONTROL_MODULE_BASE + 0x10E)
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#define CAM_XCLKA (SYSTEM_CONTROL_MODULE_BASE + 0x110)
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#define CAM_PCLK (SYSTEM_CONTROL_MODULE_BASE + 0x112)
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#define CAM_FLD (SYSTEM_CONTROL_MODULE_BASE + 0x114)
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#define CAM_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x116)
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#define CAM_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x118)
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#define CAM_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x11A)
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#define CAM_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x11C)
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#define CAM_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x11E)
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#define CAM_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x120)
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#define CAM_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x122)
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#define CAM_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x124)
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#define CAM_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x126)
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#define CAM_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x128)
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#define CAM_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x12A)
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#define CAM_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x12C)
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#define CAM_XCLKB (SYSTEM_CONTROL_MODULE_BASE + 0x12E)
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#define CAM_WEN (SYSTEM_CONTROL_MODULE_BASE + 0x130)
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#define CAM_STROBE (SYSTEM_CONTROL_MODULE_BASE + 0x132)
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#define CSI2_DX0 (SYSTEM_CONTROL_MODULE_BASE + 0x134)
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#define CSI2_DY0 (SYSTEM_CONTROL_MODULE_BASE + 0x136)
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#define CSI2_DX1 (SYSTEM_CONTROL_MODULE_BASE + 0x138)
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#define CSI2_DY1 (SYSTEM_CONTROL_MODULE_BASE + 0x13A)
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#define MCBSP2_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x13C)
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#define MCBSP2_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x13E)
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#define MCBSP2_DR (SYSTEM_CONTROL_MODULE_BASE + 0x140)
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#define MCBSP2_DX (SYSTEM_CONTROL_MODULE_BASE + 0x142)
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#define MMC1_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x144)
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#define MMC1_CMD (SYSTEM_CONTROL_MODULE_BASE + 0x146)
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#define MMC1_DAT0 (SYSTEM_CONTROL_MODULE_BASE + 0x148)
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#define MMC1_DAT1 (SYSTEM_CONTROL_MODULE_BASE + 0x14A)
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#define MMC1_DAT2 (SYSTEM_CONTROL_MODULE_BASE + 0x14C)
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#define MMC1_DAT3 (SYSTEM_CONTROL_MODULE_BASE + 0x14E)
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#define MMC1_DAT4 (SYSTEM_CONTROL_MODULE_BASE + 0x150)
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#define MMC1_DAT5 (SYSTEM_CONTROL_MODULE_BASE + 0x152)
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#define MMC1_DAT6 (SYSTEM_CONTROL_MODULE_BASE + 0x154)
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#define MMC1_DAT7 (SYSTEM_CONTROL_MODULE_BASE + 0x156)
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#define MMC2_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x158)
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#define MMC2_CMD (SYSTEM_CONTROL_MODULE_BASE + 0x15A)
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#define MMC2_DAT0 (SYSTEM_CONTROL_MODULE_BASE + 0x15C)
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#define MMC2_DAT1 (SYSTEM_CONTROL_MODULE_BASE + 0x15E)
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#define MMC2_DAT2 (SYSTEM_CONTROL_MODULE_BASE + 0x160)
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#define MMC2_DAT3 (SYSTEM_CONTROL_MODULE_BASE + 0x162)
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#define MMC2_DAT4 (SYSTEM_CONTROL_MODULE_BASE + 0x164)
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#define MMC2_DAT5 (SYSTEM_CONTROL_MODULE_BASE + 0x166)
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#define MMC2_DAT6 (SYSTEM_CONTROL_MODULE_BASE + 0x168)
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#define MMC2_DAT7 (SYSTEM_CONTROL_MODULE_BASE + 0x16A)
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#define MCBSP3_DX (SYSTEM_CONTROL_MODULE_BASE + 0x16C)
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#define MCBSP3_DR (SYSTEM_CONTROL_MODULE_BASE + 0x16E)
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#define MCBSP3_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x170)
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#define MCBSP3_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x172)
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#define UART2_CTS (SYSTEM_CONTROL_MODULE_BASE + 0x174)
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#define UART2_RTS (SYSTEM_CONTROL_MODULE_BASE + 0x176)
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#define UART2_TX (SYSTEM_CONTROL_MODULE_BASE + 0x178)
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#define UART2_RX (SYSTEM_CONTROL_MODULE_BASE + 0x17A)
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#define UART1_TX (SYSTEM_CONTROL_MODULE_BASE + 0x17C)
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#define UART1_RTS (SYSTEM_CONTROL_MODULE_BASE + 0x17E)
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#define UART1_CTS (SYSTEM_CONTROL_MODULE_BASE + 0x180)
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#define UART1_RX (SYSTEM_CONTROL_MODULE_BASE + 0x182)
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#define MCBSP4_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x184)
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#define MCBSP4_DR (SYSTEM_CONTROL_MODULE_BASE + 0x186)
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#define MCBSP4_DX (SYSTEM_CONTROL_MODULE_BASE + 0x188)
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#define MCBSP4_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x18A)
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#define MCBSP1_CLKR (SYSTEM_CONTROL_MODULE_BASE + 0x18C)
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#define MCBSP1_FSR (SYSTEM_CONTROL_MODULE_BASE + 0x18E)
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#define MCBSP1_DX (SYSTEM_CONTROL_MODULE_BASE + 0x190)
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#define MCBSP1_DR (SYSTEM_CONTROL_MODULE_BASE + 0x192)
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#define MCBSP1_CLKS (SYSTEM_CONTROL_MODULE_BASE + 0x194)
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#define MCBSP1_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x196)
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#define MCBSP1_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x198)
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#define UART3_CTS_RCTX (SYSTEM_CONTROL_MODULE_BASE + 0x19A)
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#define UART3_RTS_SD (SYSTEM_CONTROL_MODULE_BASE + 0x19C)
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#define UART3_RX_IRRX (SYSTEM_CONTROL_MODULE_BASE + 0x19E)
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#define UART3_TX_IRTX (SYSTEM_CONTROL_MODULE_BASE + 0x1A0)
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#define HSUSB0_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x1A2)
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#define HSUSB0_STP (SYSTEM_CONTROL_MODULE_BASE + 0x1A4)
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#define HSUSB0_DIR (SYSTEM_CONTROL_MODULE_BASE + 0x1A6)
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#define HSUSB0_NXT (SYSTEM_CONTROL_MODULE_BASE + 0x1A8)
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#define HSUSB0_DATA0 (SYSTEM_CONTROL_MODULE_BASE + 0x1AA)
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#define HSUSB0_DATA1 (SYSTEM_CONTROL_MODULE_BASE + 0x1AC)
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#define HSUSB0_DATA2 (SYSTEM_CONTROL_MODULE_BASE + 0x1AE)
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#define HSUSB0_DATA3 (SYSTEM_CONTROL_MODULE_BASE + 0x1B0)
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#define HSUSB0_DATA4 (SYSTEM_CONTROL_MODULE_BASE + 0x1B2)
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#define HSUSB0_DATA5 (SYSTEM_CONTROL_MODULE_BASE + 0x1B4)
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#define HSUSB0_DATA6 (SYSTEM_CONTROL_MODULE_BASE + 0x1B6)
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#define HSUSB0_DATA7 (SYSTEM_CONTROL_MODULE_BASE + 0x1B8)
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#define I2C1_SCL (SYSTEM_CONTROL_MODULE_BASE + 0x1BA)
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#define I2C1_SDA (SYSTEM_CONTROL_MODULE_BASE + 0x1BC)
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#define I2C2_SCL (SYSTEM_CONTROL_MODULE_BASE + 0x1BE)
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#define I2C2_SDA (SYSTEM_CONTROL_MODULE_BASE + 0x1C0)
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#define I2C3_SCL (SYSTEM_CONTROL_MODULE_BASE + 0x1C2)
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#define I2C3_SDA (SYSTEM_CONTROL_MODULE_BASE + 0x1C4)
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#define HDQ_SIO (SYSTEM_CONTROL_MODULE_BASE + 0x1C6)
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#define MCSPI1_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x1C8)
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#define MCSPI1_SIMO (SYSTEM_CONTROL_MODULE_BASE + 0x1CA)
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#define MCSPI1_SOMI (SYSTEM_CONTROL_MODULE_BASE + 0x1CC)
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#define MCSPI1_CS0 (SYSTEM_CONTROL_MODULE_BASE + 0x1CE)
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#define MCSPI1_CS1 (SYSTEM_CONTROL_MODULE_BASE + 0x1D0)
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#define MCSPI1_CS2 (SYSTEM_CONTROL_MODULE_BASE + 0x1D2)
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#define MCSPI1_CS3 (SYSTEM_CONTROL_MODULE_BASE + 0x1D4)
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#define MCSPI2_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x1D6)
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#define MCSPI2_SIMO (SYSTEM_CONTROL_MODULE_BASE + 0x1D8)
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#define MCSPI2_SOMI (SYSTEM_CONTROL_MODULE_BASE + 0x1DA)
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#define MCSPI2_CS0 (SYSTEM_CONTROL_MODULE_BASE + 0x1DC)
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#define MCSPI2_CS1 (SYSTEM_CONTROL_MODULE_BASE + 0x1DE)
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#define SYS_NIRQ (SYSTEM_CONTROL_MODULE_BASE + 0x1E0)
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#define SYS_CLKOUT2 (SYSTEM_CONTROL_MODULE_BASE + 0x1E2)
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#define ETK_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x5D8)
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#define ETK_CTL (SYSTEM_CONTROL_MODULE_BASE + 0x5DA)
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#define ETK_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x5DC)
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#define ETK_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x5DE)
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#define ETK_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x5E0)
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#define ETK_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x5E2)
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#define ETK_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x5E4)
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#define ETK_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x5E6)
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#define ETK_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x5E8)
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#define ETK_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x5EA)
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#define ETK_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x5EC)
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#define ETK_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x5EE)
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#define ETK_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x5F0)
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#define ETK_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x5F2)
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#define ETK_D12 (SYSTEM_CONTROL_MODULE_BASE + 0x5F4)
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#define ETK_D13 (SYSTEM_CONTROL_MODULE_BASE + 0x5F6)
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#define ETK_D14 (SYSTEM_CONTROL_MODULE_BASE + 0x5F8)
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#define ETK_D15 (SYSTEM_CONTROL_MODULE_BASE + 0x5FA)
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//Mux modes
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#define MUXMODE0 (0x0UL)
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#define MUXMODE1 (0x1UL)
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#define MUXMODE2 (0x2UL)
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#define MUXMODE3 (0x3UL)
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#define MUXMODE4 (0x4UL)
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#define MUXMODE5 (0x5UL)
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#define MUXMODE6 (0x6UL)
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#define MUXMODE7 (0x7UL)
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//Pad configuration register.
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#define PAD_CONFIG_MASK (0xFFFFUL)
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#define MUXMODE_OFFSET 0
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#define MUXMODE_MASK (0x7UL << MUXMODE_OFFSET)
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#define PULL_CONFIG_OFFSET 3
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#define PULL_CONFIG_MASK (0x3UL << PULL_CONFIG_OFFSET)
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#define INPUTENABLE_OFFSET 8
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#define INPUTENABLE_MASK (0x1UL << INPUTENABLE_OFFSET)
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#define OFFMODE_VALUE_OFFSET 9
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#define OFFMODE_VALUE_MASK (0x1FUL << OFFMODE_VALUE_OFFSET)
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#define WAKEUP_OFFSET 14
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#define WAKEUP_MASK (0x2UL << WAKEUP_OFFSET)
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#define PULLUDDISABLE (0x0UL << 0)
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#define PULLUDENABLE (0x1UL << 0)
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#define PULLTYPENOSELECT (0x0UL << 1)
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#define PULLTYPESELECT (0x1UL << 1)
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#define OUTPUT (0x0UL) //Pin is configured in output only mode.
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#define INPUT (0x1UL) //Pin is configured in bi-directional mode.
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typedef struct {
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UINTN Pin;
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UINTN MuxMode;
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UINTN PullConfig;
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UINTN InputEnable;
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} PAD_CONFIGURATION;
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#endif //__OMAP3530_PAD_CONFIGURATION_H__
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