mirror of https://github.com/acidanthera/audk.git
0f16be6d9e
https://bugzilla.tianocore.org/show_bug.cgi?id=176 Update MSR header files of processors (excluding Goldmont and Skylake processors) according to Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, September 2016, Chapter 35 Model-Specific-Registers (MSR). Summary of incompatible changes: General: 1. MSR (address 38EH) IA32_PERF_GLOBAL_STAUS in processor-specific header files has been removed or renamed to IA32_PERF_GLOBAL_STATUS Typo 'STAUS' has been fixed in SDM. If the MSR definition is the same with architectural MSR, we remove it. Otherwise, we rename the MSR. 2. MSRs (address starting from 400H) MSR_MC{X}_{XXX} (like MSR_MC4_STATUS) in processor-specific header files have been removed or renamed to IA32_MC{X}_{XXX} (like IA32_MC4_STATUS) Register name change from 'MSR_MC{X}_{XXX}' to 'IA32_MC{X}_{XXX}' in SDM. If the MSR definition is the same with architectural MSR, we remove it. Otherwise, we rename the MSR. Please note that for those MSRs still have name like 'MSR_MC{X}_{XXX}' in SDM are still kept in processor-specific header files. HaswellMsr.h: 1. MSR (address C80H) IA32_DEBUG_FEATURE has been removed Register name change from 'IA32_DEBUG_FEATURE' to 'IA32_DEBUG_INTERFACE' in SDM. Since the MSR definition is the same with architectural MSR, we remove it. SandyBridgeMsr.h: 1. MSR (address 391H) MSR_UNC_PERF_GLOBAL_CTRL, name change for bit fields 0:3 Bit description change from 'Core {X} select' to 'Slice {X} select' for bit 0:3 in SDM. SilvermontMsr.h: 1. MSR (address 2AH) MSR_EBL_CR_POWERON, structure definition changed Bit description for this MSR is totally changed in SDM, we modify the structure definition to align with it. XeonDMsr.h: 1. MSRs (address 630H to 632H) MSR_PKG_C8_RESIDENCY, MSR_PKG_C9_RESIDENCY and MSR_PKG_C10_RESIDENCY have been removed Those 3 MSRs are not defined for this processor in SDM, we remove them. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> |
||
|---|---|---|
| .. | ||
| Application/Cpuid | ||
| CpuDxe | ||
| CpuIo2Dxe | ||
| CpuIo2Smm | ||
| CpuIoPei | ||
| CpuMpPei | ||
| CpuS3DataDxe | ||
| Feature/Capsule | ||
| Include | ||
| Library | ||
| PiSmmCommunication | ||
| PiSmmCpuDxeSmm | ||
| ResetVector | ||
| SecCore | ||
| Universal/Acpi/S3Resume2Pei | ||
| Contributions.txt | ||
| License.txt | ||
| UefiCpuPkg.dec | ||
| UefiCpuPkg.dsc | ||
| UefiCpuPkg.uni | ||
| UefiCpuPkgExtra.uni | ||