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If timer interrupt is level sensitive, reloading timer compare register has a side effect of clearing GIC pending status, so a "ISB" is needed to make sure this instruction is executed before enabling CPU IRQ, or else we may get spurious timer interrupts. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>