mirror of https://github.com/acidanthera/audk.git
6e275c613e
Given that these days, our ARM port only supports ARMv7 and later, we can assume that the page table walker's memory accesses are cache coherent, and so there is no need to perform cache maintenance. It does require the page tables themselves to reside in memory mapped as writeback cacheable so ASSERT() that this is the case. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> |
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| .. | ||
| AArch64 | ||
| Arm | ||
| ArmBaseLib.inf | ||
| ArmLib.c | ||
| ArmLibPrivate.h | ||