mirror of https://github.com/acidanthera/audk.git
188 lines
5.6 KiB
C
188 lines
5.6 KiB
C
/** @file
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TPM Interface Specification definition.
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It covers both TPM1.2 and TPM2.0.
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Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _TPM_TIS_H_
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#define _TPM_TIS_H_
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//
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// Set structure alignment to 1-byte
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//
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#pragma pack (1)
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//
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// Register set map as specified in TIS specification Chapter 10
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//
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typedef struct {
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///
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/// Used to gain ownership for this particular port.
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///
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UINT8 Access; // 0
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UINT8 Reserved1[7]; // 1
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///
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/// Controls interrupts.
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///
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UINT32 IntEnable; // 8
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///
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/// SIRQ vector to be used by the TPM.
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///
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UINT8 IntVector; // 0ch
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UINT8 Reserved2[3]; // 0dh
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///
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/// What caused interrupt.
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///
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UINT32 IntSts; // 10h
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///
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/// Shows which interrupts are supported by that particular TPM.
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///
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UINT32 IntfCapability; // 14h
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///
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/// Status Register. Provides status of the TPM.
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///
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UINT8 Status; // 18h
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///
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/// Number of consecutive writes that can be done to the TPM.
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///
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UINT16 BurstCount; // 19h
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UINT8 Reserved3[9];
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///
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/// Read or write FIFO, depending on transaction.
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///
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UINT32 DataFifo; // 24h
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UINT8 Reserved4[0xed8]; // 28h
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///
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/// Vendor ID
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///
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UINT16 Vid; // 0f00h
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///
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/// Device ID
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///
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UINT16 Did; // 0f02h
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///
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/// Revision ID
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///
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UINT8 Rid; // 0f04h
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UINT8 Reserved[0x7b]; // 0f05h
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///
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/// Alias to I/O legacy space.
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///
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UINT32 LegacyAddress1; // 0f80h
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///
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/// Additional 8 bits for I/O legacy space extension.
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///
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UINT32 LegacyAddress1Ex; // 0f84h
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///
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/// Alias to second I/O legacy space.
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///
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UINT32 LegacyAddress2; // 0f88h
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///
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/// Additional 8 bits for second I/O legacy space extension.
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///
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UINT32 LegacyAddress2Ex; // 0f8ch
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///
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/// Vendor-defined configuration registers.
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///
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UINT8 VendorDefined[0x70];// 0f90h
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} TIS_PC_REGISTERS;
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//
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// Restore original structure alignment
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//
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#pragma pack ()
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//
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// Define pointer types used to access TIS registers on PC
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//
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typedef TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR;
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//
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// Define bits of ACCESS and STATUS registers
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//
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///
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/// This bit is a 1 to indicate that the other bits in this register are valid.
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///
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#define TIS_PC_VALID BIT7
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///
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/// Indicate that this locality is active.
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///
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#define TIS_PC_ACC_ACTIVE BIT5
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///
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/// Set to 1 to indicate that this locality had the TPM taken away while
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/// this locality had the TIS_PC_ACC_ACTIVE bit set.
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///
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#define TIS_PC_ACC_SEIZED BIT4
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///
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/// Set to 1 to indicate that TPM MUST reset the
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/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the
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/// locality that is writing this bit.
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///
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#define TIS_PC_ACC_SEIZE BIT3
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///
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/// When this bit is 1, another locality is requesting usage of the TPM.
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///
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#define TIS_PC_ACC_PENDIND BIT2
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///
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/// Set to 1 to indicate that this locality is requesting to use TPM.
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///
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#define TIS_PC_ACC_RQUUSE BIT1
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///
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/// A value of 1 indicates that a T/OS has not been established on the platform
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///
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#define TIS_PC_ACC_ESTABLISH BIT0
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///
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/// Write a 1 to this bit to notify TPM to cancel currently executing command
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///
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#define TIS_PC_STS_CANCEL BIT24
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///
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/// This field indicates that STS_DATA and STS_EXPECT are valid
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///
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#define TIS_PC_STS_VALID BIT7
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///
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/// When this bit is 1, TPM is in the Ready state,
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/// indicating it is ready to receive a new command.
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///
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#define TIS_PC_STS_READY BIT6
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///
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/// Write a 1 to this bit to cause the TPM to execute that command.
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///
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#define TIS_PC_STS_GO BIT5
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///
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/// This bit indicates that the TPM has data available as a response.
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///
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#define TIS_PC_STS_DATA BIT4
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///
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/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.
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///
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#define TIS_PC_STS_EXPECT BIT3
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///
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/// Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command.
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///
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#define TIS_PC_STS_SELFTEST_DONE BIT2
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///
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/// Writes a 1 to this bit to force the TPM to re-send the response.
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///
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#define TIS_PC_STS_RETRY BIT1
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//
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// Default TimeOut value
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//
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#define TIS_TIMEOUT_A (750 * 1000) // 750ms
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#define TIS_TIMEOUT_B (2000 * 1000) // 2s
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#define TIS_TIMEOUT_C (750 * 1000) // 750ms
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#define TIS_TIMEOUT_D (750 * 1000) // 750ms
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#endif
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