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81a23a0fee
Remove the references to DuetPkg. Copy the files from revision ffea0a2ce21e8e9878587de2419959a7bfea4021 of DuetPkg into CorebootModulePkg. The components include: * PciBusNoEnumerationDxe * PciRootBridgeNoEnumerationDxe * SataControllerDxe TEST=Build and run on Galileo Gen2 Change-Id: Id07185f7e226749e5f7c6b6cb427bcef7eac8496 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
168 lines
4.2 KiB
C
168 lines
4.2 KiB
C
/*++
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Copyright (c) 2005 - 2006, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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PciCommand.h
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Abstract:
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PCI Bus Driver
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Revision History
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--*/
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#ifndef _EFI_PCI_COMMAND_H
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#define _EFI_PCI_COMMAND_H
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#include "PciBus.h"
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//
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// The PCI Command register bits owned by PCI Bus driver.
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//
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// They should be cleared at the beginning. The other registers
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// are owned by chipset, we should not touch them.
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//
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#define EFI_PCI_COMMAND_BITS_OWNED ( \
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EFI_PCI_COMMAND_IO_SPACE | \
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EFI_PCI_COMMAND_MEMORY_SPACE | \
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EFI_PCI_COMMAND_BUS_MASTER | \
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EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE | \
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EFI_PCI_COMMAND_VGA_PALETTE_SNOOP | \
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EFI_PCI_COMMAND_FAST_BACK_TO_BACK \
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)
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//
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// The PCI Bridge Control register bits owned by PCI Bus driver.
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//
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// They should be cleared at the beginning. The other registers
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// are owned by chipset, we should not touch them.
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//
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#define EFI_PCI_BRIDGE_CONTROL_BITS_OWNED ( \
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EFI_PCI_BRIDGE_CONTROL_ISA | \
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EFI_PCI_BRIDGE_CONTROL_VGA | \
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EFI_PCI_BRIDGE_CONTROL_VGA_16 | \
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EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK \
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)
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//
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// The PCCard Bridge Control register bits owned by PCI Bus driver.
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//
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// They should be cleared at the beginning. The other registers
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// are owned by chipset, we should not touch them.
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//
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#define EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED ( \
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EFI_PCI_BRIDGE_CONTROL_ISA | \
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EFI_PCI_BRIDGE_CONTROL_VGA | \
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EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK \
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)
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EFI_STATUS
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PciReadCommandRegister (
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IN PCI_IO_DEVICE *PciIoDevice,
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OUT UINT16 *Command
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);
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EFI_STATUS
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PciSetCommandRegister (
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IN PCI_IO_DEVICE *PciIoDevice,
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IN UINT16 Command
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);
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EFI_STATUS
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PciEnableCommandRegister (
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IN PCI_IO_DEVICE *PciIoDevice,
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IN UINT16 Command
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);
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EFI_STATUS
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PciDisableCommandRegister (
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IN PCI_IO_DEVICE *PciIoDevice,
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IN UINT16 Command
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);
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EFI_STATUS
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PciDisableBridgeControlRegister (
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IN PCI_IO_DEVICE *PciIoDevice,
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IN UINT16 Command
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);
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EFI_STATUS
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PciEnableBridgeControlRegister (
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IN PCI_IO_DEVICE *PciIoDevice,
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IN UINT16 Command
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);
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EFI_STATUS
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PciReadBridgeControlRegister (
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IN PCI_IO_DEVICE *PciIoDevice,
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OUT UINT16 *Command
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);
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BOOLEAN
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PciCapabilitySupport (
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IN PCI_IO_DEVICE *PciIoDevice
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)
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/*++
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Routine Description:
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TODO: Add function description
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Arguments:
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PciIoDevice - TODO: add argument description
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Returns:
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TODO: add return values
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--*/
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;
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EFI_STATUS
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LocateCapabilityRegBlock (
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IN PCI_IO_DEVICE *PciIoDevice,
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IN UINT8 CapId,
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IN OUT UINT8 *Offset,
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OUT UINT8 *NextRegBlock OPTIONAL
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)
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/*++
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Routine Description:
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Locate Capability register.
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Arguments:
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PciIoDevice - A pointer to the PCI_IO_DEVICE.
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CapId - The capability ID.
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Offset - A pointer to the offset.
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As input: the default offset;
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As output: the offset of the found block.
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NextRegBlock - An optional pointer to return the value of next block.
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Returns:
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EFI_UNSUPPORTED - The Pci Io device is not supported.
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EFI_NOT_FOUND - The Pci Io device cannot be found.
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EFI_SUCCESS - The Pci Io device is successfully located.
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--*/
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;
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#endif
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