mirror of
https://github.com/acidanthera/audk.git
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251 lines
8.5 KiB
C
251 lines
8.5 KiB
C
/** @file
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Copyright (c) 2024, Mikhail Krichanov. All rights reserved.
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SPDX-License-Identifier: BSD-3-Clause
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**/
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#include "DxeMain.h"
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#include <Register/Intel/ArchitecturalMsr.h>
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#include <IndustryStandard/PageTable.h>
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VOID
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EFIAPI
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MakeUserPageTableTemplate (
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OUT VOID **UserPageTableTemplate,
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OUT UINTN *UserPageTableTemplateSize
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)
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{
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EFI_HOB_GUID_TYPE *GuidHob;
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EFI_PAGE_TABLE_INFO *PageTableInfo;
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UINTN BigPageAddress;
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EFI_PHYSICAL_ADDRESS PageAddress;
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UINTN IndexOfPml5Entries;
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UINTN IndexOfPml4Entries;
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UINTN IndexOfPdpEntries;
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UINTN IndexOfPageDirectoryEntries;
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PAGE_MAP_AND_DIRECTORY_POINTER *PageMapLevel5Entry;
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PAGE_MAP_AND_DIRECTORY_POINTER *PageMapLevel4Entry;
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PAGE_MAP_AND_DIRECTORY_POINTER *PageMap;
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PAGE_MAP_AND_DIRECTORY_POINTER *PageDirectoryPointerEntry;
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PAGE_TABLE_ENTRY *PageDirectoryEntry;
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PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry;
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GuidHob = GetFirstGuidHob (&gEfiHobPageTableInfoGuid);
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if (GuidHob == NULL) {
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DEBUG ((DEBUG_ERROR, "Core: Could not retrieve PageTableInfo HOB.\n"));
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CpuDeadLoop ();
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}
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PageTableInfo = (EFI_PAGE_TABLE_INFO *)(GET_GUID_HOB_DATA (GuidHob));
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BigPageAddress = (UINTN)AllocateAlignedPages (PageTableInfo->TotalPagesNum, PAGE_TABLE_POOL_ALIGNMENT);
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if (BigPageAddress == 0) {
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DEBUG ((DEBUG_ERROR, "Core: Could not allocate buffer for User page table.\n"));
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CpuDeadLoop ();
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}
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//
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// By architecture only one PageMapLevel4 exists - so lets allocate storage for it.
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//
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PageMap = (VOID *)BigPageAddress;
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if (PageTableInfo->Page5LevelEnabled) {
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//
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// By architecture only one PageMapLevel5 exists - so lets allocate storage for it.
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//
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PageMapLevel5Entry = PageMap;
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BigPageAddress += SIZE_4KB;
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}
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PageAddress = 0;
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for ( IndexOfPml5Entries = 0
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; IndexOfPml5Entries < PageTableInfo->NumberOfPml5EntriesNeeded
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; IndexOfPml5Entries++)
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{
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//
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// Each PML5 entry points to a page of PML4 entires.
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// So lets allocate space for them and fill them in in the IndexOfPml4Entries loop.
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// When 5-Level Paging is disabled, below allocation happens only once.
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//
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PageMapLevel4Entry = (VOID *)BigPageAddress;
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BigPageAddress += SIZE_4KB;
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if (PageTableInfo->Page5LevelEnabled) {
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//
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// Make a PML5 Entry
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//
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PageMapLevel5Entry->Uint64 = (UINT64)(UINTN)PageMapLevel4Entry | PageTableInfo->AddressEncMask;
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PageMapLevel5Entry->Bits.ReadWrite = 1;
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PageMapLevel5Entry->Bits.UserSupervisor = 1;
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PageMapLevel5Entry->Bits.Present = 1;
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PageMapLevel5Entry++;
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}
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for ( IndexOfPml4Entries = 0
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; IndexOfPml4Entries < (PageTableInfo->NumberOfPml5EntriesNeeded == 1 ? PageTableInfo->NumberOfPml4EntriesNeeded : 512)
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; IndexOfPml4Entries++, PageMapLevel4Entry++)
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{
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//
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// Each PML4 entry points to a page of Page Directory Pointer entires.
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// So lets allocate space for them and fill them in in the IndexOfPdpEntries loop.
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//
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PageDirectoryPointerEntry = (VOID *)BigPageAddress;
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BigPageAddress += SIZE_4KB;
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//
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// Make a PML4 Entry
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//
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PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry | PageTableInfo->AddressEncMask;
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PageMapLevel4Entry->Bits.ReadWrite = 1;
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PageMapLevel4Entry->Bits.UserSupervisor = 1;
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PageMapLevel4Entry->Bits.Present = 1;
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if (PageTableInfo->Page1GSupport) {
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PageDirectory1GEntry = (VOID *)PageDirectoryPointerEntry;
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for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress += SIZE_1GB) {
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//
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// Fill in the Page Directory entries
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//
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PageDirectory1GEntry->Uint64 = (UINT64)PageAddress | PageTableInfo->AddressEncMask;
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PageDirectory1GEntry->Bits.ReadWrite = 1;
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PageDirectory1GEntry->Bits.Present = 1;
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PageDirectory1GEntry->Bits.MustBe1 = 1;
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}
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} else {
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for ( IndexOfPdpEntries = 0
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; IndexOfPdpEntries < (PageTableInfo->NumberOfPml4EntriesNeeded == 1 ? PageTableInfo->NumberOfPdpEntriesNeeded : 512)
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; IndexOfPdpEntries++, PageDirectoryPointerEntry++)
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{
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//
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// Each Directory Pointer entries points to a page of Page Directory entires.
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// So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.
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//
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PageDirectoryEntry = (VOID *)BigPageAddress;
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BigPageAddress += SIZE_4KB;
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//
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// Fill in a Page Directory Pointer Entries
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//
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PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry | PageTableInfo->AddressEncMask;
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PageDirectoryPointerEntry->Bits.ReadWrite = 1;
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PageDirectoryPointerEntry->Bits.UserSupervisor = 1;
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PageDirectoryPointerEntry->Bits.Present = 1;
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for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += SIZE_2MB) {
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//
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// Fill in the Page Directory entries
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//
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PageDirectoryEntry->Uint64 = (UINT64)PageAddress | PageTableInfo->AddressEncMask;
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PageDirectoryEntry->Bits.ReadWrite = 1;
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PageDirectoryEntry->Bits.Present = 0;
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PageDirectoryEntry->Bits.MustBe1 = 1;
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}
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}
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//
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// Fill with null entry for unused PDPTE
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//
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ZeroMem (PageDirectoryPointerEntry, (512 - IndexOfPdpEntries) * sizeof (PAGE_MAP_AND_DIRECTORY_POINTER));
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}
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}
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//
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// For the PML4 entries we are not using fill in a null entry.
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//
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ZeroMem (PageMapLevel4Entry, (512 - IndexOfPml4Entries) * sizeof (PAGE_MAP_AND_DIRECTORY_POINTER));
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}
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if (PageTableInfo->Page5LevelEnabled) {
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//
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// For the PML5 entries we are not using fill in a null entry.
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//
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ZeroMem (PageMapLevel5Entry, (512 - IndexOfPml5Entries) * sizeof (PAGE_MAP_AND_DIRECTORY_POINTER));
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}
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*UserPageTableTemplate = (VOID *)PageMap;
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*UserPageTableTemplateSize = ALIGN_VALUE (EFI_PAGES_TO_SIZE (PageTableInfo->TotalPagesNum), PAGE_TABLE_POOL_ALIGNMENT);
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SetUefiImageMemoryAttributes ((UINT64)PageMap, *UserPageTableTemplateSize, EFI_MEMORY_XP);
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}
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VOID
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EFIAPI
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InitializeMsr (
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IN OUT EFI_CONFIGURATION_TABLE *Table,
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IN UINTN NumberOfEntries
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)
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{
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UINT64 Msr;
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IA32_CR4 Cr4;
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IA32_EFLAGS32 Eflags;
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UINT32 Ebx;
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UINT32 Edx;
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MSR_IA32_EFER_REGISTER MsrEfer;
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Ebx = 0;
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Edx = 0;
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//
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// Forbid global pages.
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//
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Cr4.UintN = AsmReadCr4 ();
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Cr4.Bits.PGE = 0;
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AsmWriteCr4 (Cr4.UintN);
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//
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// Forbid supervisor-mode accesses to any user-mode pages.
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//
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AsmCpuidEx (0x07, 0x0, NULL, &Ebx, NULL, NULL);
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if ((Ebx & BIT7) != 0) {
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Cr4.UintN = AsmReadCr4 ();
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Cr4.Bits.SMEP = 1;
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AsmWriteCr4 (Cr4.UintN);
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Eflags.UintN = AsmReadEflags ();
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Eflags.Bits.AC = 0;
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AsmWriteEflags (Eflags.UintN);
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}
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if ((Ebx & BIT20) != 0) {
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Cr4.UintN = AsmReadCr4 ();
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Cr4.Bits.SMAP = 1;
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AsmWriteCr4 (Cr4.UintN);
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Eflags.UintN = AsmReadEflags ();
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Eflags.Bits.AC = 0;
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AsmWriteEflags (Eflags.UintN);
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}
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//
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// Enable SYSCALL and SYSRET.
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//
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AsmCpuidEx (0x80000001, 0x0, NULL, NULL, NULL, &Edx);
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if ((Edx & BIT11) != 0) {
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MsrEfer.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);
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MsrEfer.Bits.SCE = 1;
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AsmWriteMsr64 (MSR_IA32_EFER, MsrEfer.Uint64);
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} else {
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DEBUG ((DEBUG_ERROR, "Core: SYSCALL and SYSRET are not supported.\n"));
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CpuDeadLoop ();
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}
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//
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// Initialize MSR_IA32_STAR, MSR_IA32_LSTAR and MSR_IA32_FMASK for SYSCALL and SYSRET.
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//
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Msr = (((((UINT64)RING3_CODE64_SEL - 16) | 3) << 16) | (UINT64)RING0_CODE64_SEL) << 32;
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AsmWriteMsr64 (MSR_IA32_STAR, Msr);
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Msr = (UINT64)(UINTN)CoreBootServices;
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AsmWriteMsr64 (MSR_IA32_LSTAR, Msr);
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//
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// Disable maskable interrupts at SYSCALL.
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//
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Msr = (UINT64)BIT9;
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AsmWriteMsr64 (MSR_IA32_FMASK, Msr);
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gCorePageTable = AsmReadCr3 ();
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}
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