Yao, Jiewen 8e496a7abc Always set WP in CR0. ... Always set RW+P bit for page table by default. So that we can use write-protection for code later. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com> Reviewed-by: "Kinney, Michael D" <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18960 6f19259b-4bc3-4df7-8a09-765794883524		2015-11-26 07:01:08 +00:00
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Ia32	Always set WP in CR0.	2015-11-26 07:01:08 +00:00
X64	Always set WP in CR0.	2015-11-26 07:01:08 +00:00
CpuS3.c	…
CpuService.c	…
CpuService.h	…
MpService.c	Always set WP in CR0.	2015-11-26 07:01:08 +00:00
PiSmmCpuDxeSmm.c	Add 2 APIs in SmmCpuFeaturesLib.	2015-11-26 04:12:53 +00:00
PiSmmCpuDxeSmm.h	Always set WP in CR0.	2015-11-26 07:01:08 +00:00
PiSmmCpuDxeSmm.inf	Eliminate EFI_IMAGE_MACHINE_TYPE_SUPPORTED.	2015-11-25 04:23:01 +00:00
PiSmmCpuDxeSmm.uni	…
PiSmmCpuDxeSmmExtra.uni	…
SmmProfile.c	Always set WP in CR0.	2015-11-26 07:01:08 +00:00
SmmProfile.h	…
SmmProfileInternal.h	…
SmramSaveState.c	…
SyncTimer.c	…