mirror of https://github.com/acidanthera/audk.git
48 lines
1.1 KiB
C
48 lines
1.1 KiB
C
/** @file
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CXL 3.1 definitions
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This file contains the register definitions and firmware interface based
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on the Compute Express Link (CXL) Specification Revision 3.1.
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Copyright (c) 2024, Phytium Technology Co Ltd. All rights reserved.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@par Reference(s):
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- Compute Express Link (CXL) Specification Revision 3.1.
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(https://computeexpresslink.org/cxl-specification/)
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**/
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#ifndef CXL31_H_
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#define CXL31_H_
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#include <IndustryStandard/Cxl30.h>
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//
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// "CEDT" CXL Early Discovery Table
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// Compute Express Link Specification Revision 3.1 - Chapter 9.18.1
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//
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#define CXL_EARLY_DISCOVERY_TABLE_REVISION_02 0x2
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#define CEDT_TYPE_CSDS 0x4
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//
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// Ensure proper structure formats
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//
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#pragma pack(1)
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//
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// Definition for CXL System Description Structure (CSDS)
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// Compute Express Link Specification Revision 3.1 - Chapter 9.18.6
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//
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typedef struct {
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CEDT_STRUCTURE Header;
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UINT16 Capabilities;
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UINT16 Reserved;
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} CXL_DOWNSTREAM_PORT_ASSOCIATION_STRUCTURE;
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#pragma pack()
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#endif
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