mirror of https://github.com/acidanthera/audk.git
9f75aacc7a
"Main.asm" calls TransitionFromReal16To32BitFlat (and does some other
things) before it jumps to the platform's SEC entry point.
TransitionFromReal16To32BitFlat enters big real mode, and sets the DS, ES,
FS, GS, and SS registers to offset ("selector") LINEAR_SEL in the GDT
(defined in "UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm"). The
GDT entry ("segment descriptor") at LINEAR_SEL defines a segment covering
the full 32-bit address space, meant for "read/write data".
Document this fact for all the affected segment registers, as output
parameters for TransitionFromReal16To32BitFlat, saying "Selector allowing
flat access to all addresses".
For 64-bit SEC, "Main.asm" calls Transition32FlatTo64Flat in addition,
between calling TransitionFromReal16To32BitFlat and jumping to the SEC
entry point. Transition32FlatTo64Flat enters long mode. In long mode,
segmentation is largely ignored:
- all segments are considered flat (covering the whole 64-bit address
space),
- with the (possible) exception of FS and GS, whose bases can still be
changed, albeit with new methods, not through the GDT. (Through the
IA32_FS_BASE and IA32_GS_BASE Model Specific Registers, and/or the
WRFSBASE, WRGSBASE and SWAPGS instructions.)
Thus, document the segment registers with the same "Selector allowing flat
access to all addresses" language on the "Main.asm" level too, since that
is valid for both 32-bit and 64-bit modes.
(Technically, "Main.asm" does not return, but RBP/EBP, passed similarly to
the SEC entry point, is already documented as an output parameter.)
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Suggested-by: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
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||
|---|---|---|
| .. | ||
| Bin | ||
| Ia16 | ||
| Ia32 | ||
| Tools | ||
| X64 | ||
| Build.py | ||
| CommonMacros.inc | ||
| DebugDisabled.asm | ||
| Main.asm | ||
| Port80Debug.asm | ||
| PostCodes.inc | ||
| ReadMe.txt | ||
| ResetVector.uni | ||
| ResetVectorExtra.uni | ||
| SerialDebug.asm | ||
| Vtf0.inf | ||
| Vtf0.nasmb | ||
ReadMe.txt
=== HOW TO USE VTF0 === Add this line to your FDF FV section: INF RuleOverride=RESET_VECTOR USE = IA32 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf (For X64 SEC/PEI change IA32 to X64 => 'USE = X64') In your FDF FFS file rules sections add: [Rule.Common.SEC.RESET_VECTOR] FILE RAW = $(NAMED_GUID) { RAW RAW |.raw } === VTF0 Boot Flow === 1. Transition to IA32 flat mode 2. Locate BFV (Boot Firmware Volume) by checking every 4kb boundary 3. Locate SEC image 4. X64 VTF0 transitions to X64 mode 5. Call SEC image entry point == VTF0 SEC input parameters == All inputs to SEC image are register based: EAX/RAX - Initial value of the EAX register (BIST: Built-in Self Test) DI - 'BP': boot-strap processor, or 'AP': application processor EBP/RBP - Pointer to the start of the Boot Firmware Volume === HOW TO BUILD VTF0 === Dependencies: * Python 2.5~2.7 * Nasm 2.03 or newer To rebuild the VTF0 binaries: 1. Change to VTF0 source dir: UefiCpuPkg/ResetVector/Vtf0 2. nasm and python should be in executable path 3. Run this command: python Build.py 4. Binaries output will be in UefiCpuPkg/ResetVector/Vtf0/Bin