mirror of https://github.com/acidanthera/audk.git
202 lines
3.8 KiB
C
202 lines
3.8 KiB
C
/** @file
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef __ARM_V7_H__
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#define __ARM_V7_H__
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#include <Chipset/ArmV7Mmu.h>
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// Domain Access Control Register
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#define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))
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#define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a)))
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#define DOMAIN_ACCESS_CONTROL_CLIENT(a) (1UL << (2 * (a)))
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#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))
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#define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))
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// Cortex A9 feature bit definitions
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#define A9_FEATURE_PARITY (1<<9)
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#define A9_FEATURE_AOW (1<<8)
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#define A9_FEATURE_EXCL (1<<7)
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#define A9_FEATURE_SMP (1<<6)
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#define A9_FEATURE_FOZ (1<<3)
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#define A9_FEATURE_DPREF (1<<2)
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#define A9_FEATURE_HINT (1<<1)
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#define A9_FEATURE_FWD (1<<0)
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// SCU register offsets & masks
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#define SCU_CONTROL_OFFSET 0x0
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#define SCU_CONFIG_OFFSET 0x4
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#define SCU_INVALL_OFFSET 0xC
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#define SCU_FILT_START_OFFSET 0x40
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#define SCU_FILT_END_OFFSET 0x44
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#define SCU_SACR_OFFSET 0x50
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#define SCU_SSACR_OFFSET 0x54
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#define SMP_GIC_CPUIF_BASE 0x100
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#define SMP_GIC_DIST_BASE 0x1000
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// CPACR - Coprocessor Access Control Register definitions
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#define CPACR_CP_DENIED(cp) 0x00
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#define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)
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#define CPACR_CP_FULL(cp) ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)
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#define CPACR_ASEDIS (1 << 31)
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#define CPACR_D32DIS (1 << 30)
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#define CPACR_CP_FULL_ACCESS 0x0FFFFFFF
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// NSACR - Non-Secure Access Control Register definitions
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#define NSACR_CP(cp) ((1 << (cp)) & 0x3FFF)
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#define NSACR_NSD32DIS (1 << 14)
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#define NSACR_NSASEDIS (1 << 15)
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#define NSACR_PLE (1 << 16)
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#define NSACR_TL (1 << 17)
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#define NSACR_NS_SMP (1 << 18)
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#define NSACR_RFR (1 << 19)
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// SCR - Secure Configuration Register definitions
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#define SCR_NS (1 << 0)
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#define SCR_IRQ (1 << 1)
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#define SCR_FIQ (1 << 2)
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#define SCR_EA (1 << 3)
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#define SCR_FW (1 << 4)
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#define SCR_AW (1 << 5)
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VOID
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EFIAPI
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ArmEnableSWPInstruction (
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VOID
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);
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VOID
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EFIAPI
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ArmWriteNsacr (
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IN UINT32 SetWayFormat
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);
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VOID
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EFIAPI
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ArmWriteScr (
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IN UINT32 SetWayFormat
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);
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VOID
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EFIAPI
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ArmWriteVMBar (
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IN UINT32 SetWayFormat
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);
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VOID
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EFIAPI
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ArmWriteVBar (
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IN UINT32 SetWayFormat
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);
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UINT32
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EFIAPI
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ArmReadVBar (
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VOID
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);
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VOID
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EFIAPI
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ArmWriteCPACR (
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IN UINT32 SetWayFormat
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);
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VOID
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EFIAPI
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ArmEnableVFP (
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VOID
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);
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VOID
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EFIAPI
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ArmCallWFI (
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VOID
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);
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VOID
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EFIAPI
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ArmInvalidScu (
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VOID
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);
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UINTN
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EFIAPI
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ArmGetScuBaseAddress (
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VOID
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);
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UINT32
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EFIAPI
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ArmIsScuEnable (
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VOID
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);
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VOID
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EFIAPI
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ArmWriteAuxCr (
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IN UINT32 Bit
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);
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UINT32
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EFIAPI
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ArmReadAuxCr (
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VOID
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);
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VOID
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EFIAPI
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ArmSetAuxCrBit (
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IN UINT32 Bits
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);
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VOID
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EFIAPI
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ArmSetupSmpNonSecure (
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IN UINTN CoreId
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);
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UINTN
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EFIAPI
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ArmReadCbar (
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VOID
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);
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VOID
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EFIAPI
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ArmInvalidateInstructionAndDataTlb (
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VOID
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);
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UINTN
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EFIAPI
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ArmReadMpidr (
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VOID
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);
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UINTN
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EFIAPI
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ArmReadTpidrurw (
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VOID
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);
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VOID
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EFIAPI
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ArmWriteTpidrurw (
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UINTN Value
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);
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#endif // __ARM_V7_H__
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