mirror of https://github.com/acidanthera/audk.git
df67a480eb
When source level debug is enabled, but debug cable is not connected,
XhcResetHC() in XhciReg.c will reset the host controller, the debug
capability registers will be also reset. After the code in
InitializeUsbDebugHardware() sets DCE bit and LSE bit to "1" in DCCTRL,
there will be DMA on 0 (the value of some debug capability registers
for data transfer is 0) address buffer, fault info like below will
appear when IOMMU based on VTd is enabled.
VER_REG - 0x00000010
CAP_REG - 0x00D2008C40660462
ECAP_REG - 0x0000000000F050DA
GSTS_REG - 0xC0000000
RTADDR_REG - 0x0000000086512000
CCMD_REG - 0x2800000000000000
FSTS_REG - 0x00000002
FECTL_REG - 0xC0000000
FEDATA_REG - 0x00000000
FEADDR_REG - 0x00000000
FEUADDR_REG - 0x00000000
FRCD_REG[0] - 0xC0000006000000A0 0000000000000000
Fault Info - 0x0000000000000000
Source - B00 D14 F00
Type - 1 (read)
Reason - 6
IVA_REG - 0x0000000000000000
IOTLB_REG - 0x1200000000000000
This patch is to return error for the case.
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Hao Wu <hao.a.wu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
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|---|---|---|
| .. | ||
| DebugCommunicationLibUsb3Common.c | ||
| DebugCommunicationLibUsb3Dxe.c | ||
| DebugCommunicationLibUsb3Dxe.inf | ||
| DebugCommunicationLibUsb3Dxe.uni | ||
| DebugCommunicationLibUsb3Internal.h | ||
| DebugCommunicationLibUsb3Pei.c | ||
| DebugCommunicationLibUsb3Pei.inf | ||
| DebugCommunicationLibUsb3Pei.uni | ||
| DebugCommunicationLibUsb3Transfer.c | ||