mirror of https://github.com/acidanthera/audk.git
225 lines
6.8 KiB
C
225 lines
6.8 KiB
C
/*++
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Copyright (c) 2005 - 2006, Intel Corporation
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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PcatPciRootBridge.h
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Abstract:
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The driver for the host to pci bridge (root bridge).
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--*/
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#ifndef _PCAT_PCI_ROOT_BRIDGE_H_
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#define _PCAT_PCI_ROOT_BRIDGE_H_
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#include <PiDxe.h>
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#include <Protocol/PciRootBridgeIo.h>
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#include <Protocol/DeviceIo.h>
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#include <Protocol/CpuIo.h>
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#include <Library/UefiLib.h>
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#include <Library/BaseLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DevicePathLib.h>
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#include <Library/HobLib.h>
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#include <Guid/PciOptionRomTable.h>
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#include <Guid/HobList.h>
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#include <Guid/PciExpressBaseAddress.h>
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#include <IndustryStandard/Acpi.h>
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#include <IndustryStandard/Pci.h>
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#define PCI_MAX_SEGMENT 0
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//
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// Driver Instance Data Prototypes
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//
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#define PCAT_PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32('p', 'c', 'r', 'b')
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typedef struct {
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UINT32 Signature;
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EFI_HANDLE Handle;
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EFI_DEVICE_PATH_PROTOCOL *DevicePath;
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io;
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EFI_CPU_IO_PROTOCOL *CpuIo;
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UINT32 RootBridgeNumber;
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UINT32 PrimaryBus;
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UINT32 SubordinateBus;
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UINT64 MemBase; // Offsets host to bus memory addr.
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UINT64 MemLimit; // Max allowable memory access
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UINT64 IoBase; // Offsets host to bus io addr.
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UINT64 IoLimit; // Max allowable io access
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UINT64 PciAddress;
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UINT64 PciData;
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UINT64 PhysicalMemoryBase;
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UINT64 PhysicalIoBase;
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EFI_LOCK PciLock;
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UINT64 Attributes;
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UINT64 Mem32Base;
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UINT64 Mem32Limit;
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UINT64 Pmem32Base;
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UINT64 Pmem32Limit;
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UINT64 Mem64Base;
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UINT64 Mem64Limit;
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UINT64 Pmem64Base;
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UINT64 Pmem64Limit;
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UINT64 PciExpressBaseAddress;
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EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;
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LIST_ENTRY MapInfo;
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} PCAT_PCI_ROOT_BRIDGE_INSTANCE;
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//
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// Driver Instance Data Macros
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//
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#define DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) \
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CR(a, PCAT_PCI_ROOT_BRIDGE_INSTANCE, Io, PCAT_PCI_ROOT_BRIDGE_SIGNATURE)
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//
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// Private data types
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//
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typedef union {
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UINT8 volatile *buf;
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UINT8 volatile *ui8;
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UINT16 volatile *ui16;
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UINT32 volatile *ui32;
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UINT64 volatile *ui64;
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UINTN volatile ui;
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} PTR;
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typedef struct {
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation;
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UINTN NumberOfBytes;
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UINTN NumberOfPages;
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EFI_PHYSICAL_ADDRESS HostAddress;
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EFI_PHYSICAL_ADDRESS MappedHostAddress;
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} MAP_INFO;
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typedef struct {
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LIST_ENTRY Link;
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MAP_INFO * Map;
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} MAP_INFO_INSTANCE;
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typedef
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VOID
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(*EFI_PCI_BUS_SCAN_CALLBACK) (
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,
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UINT16 MinBus,
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UINT16 MaxBus,
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UINT16 MinDevice,
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UINT16 MaxDevice,
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UINT16 MinFunc,
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UINT16 MaxFunc,
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UINT16 Bus,
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UINT16 Device,
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UINT16 Func,
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IN VOID *Context
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);
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typedef struct {
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UINT16 *CommandRegisterBuffer;
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UINT32 PpbMemoryWindow;
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} PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT;
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typedef struct {
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UINT8 Register;
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UINT8 Function;
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UINT8 Device;
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UINT8 Bus;
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UINT8 Reserved[4];
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} DEFIO_PCI_ADDR;
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//
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// Driver Protocol Constructor Prototypes
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//
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EFI_STATUS
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ConstructConfiguration(
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IN OUT PCAT_PCI_ROOT_BRIDGE_INSTANCE *PrivateData
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);
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EFI_STATUS
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PcatPciRootBridgeParseBars (
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IN PCAT_PCI_ROOT_BRIDGE_INSTANCE *PrivateData,
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IN UINT16 Command,
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IN UINTN Bus,
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IN UINTN Device,
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IN UINTN Function
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);
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EFI_STATUS
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ScanPciRootBridgeForRoms(
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev
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);
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EFI_STATUS
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PcatRootBridgeDevicePathConstructor (
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IN EFI_DEVICE_PATH_PROTOCOL **Protocol,
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IN UINTN RootBridgeNumber,
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IN BOOLEAN IsPciExpress
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);
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EFI_STATUS
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PcatRootBridgeIoConstructor (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol,
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IN UINTN SegmentNumber
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);
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EFI_STATUS
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PcatRootBridgeIoGetIoPortMapping (
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OUT EFI_PHYSICAL_ADDRESS *IoPortMapping,
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OUT EFI_PHYSICAL_ADDRESS *MemoryPortMapping
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);
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EFI_STATUS
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PcatRootBridgeIoPciRW (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
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IN BOOLEAN Write,
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
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IN UINT64 UserAddress,
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IN UINTN Count,
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IN OUT VOID *UserBuffer
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);
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UINT64
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GetPciExpressBaseAddressForRootBridge (
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IN UINTN HostBridgeNumber,
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IN UINTN RootBridgeNumber
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);
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//
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// Driver entry point prototype
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//
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EFI_STATUS
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EFIAPI
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InitializePcatPciRootBridge (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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);
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extern EFI_CPU_IO_PROTOCOL *gCpuIo;
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#endif
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