audk/IntelSiliconPkg/Feature/VTd/IntelVTdDxe
Star Zeng bac7f02365 IntelSiliconPkg IntelVTdDxe: Fix flush cache issue
The patch fixes flush cache issue in
CreateSecondLevelPagingEntryTable().

We found some video cards still not work even they have
been added to the exception list.

In CreateSecondLevelPagingEntryTable(), the check
"(BaseAddress >= MemoryLimit)" may be TRUE and "goto Done"
will be executed, then the FlushPageTableMemory operations
at the end of the function will be skipped.

Instead of "goto Done", this patch uses "break" to break
the for loops, then the FlushPageTableMemory operations
at the end of the function could have opportunity to be
executed.

The patch also fixes a miscalculation for Lvl3End.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2018-01-24 18:40:36 +08:00
..
BmDma.c IntelSiliconPkg IntelVTdDxe: Use TPL to protect list/engine operation 2018-01-05 10:26:33 +08:00
DmaProtection.c IntelSiliconPkg IntelVTdDxe: Support early SetAttributes() 2018-01-05 10:26:34 +08:00
DmaProtection.h IntelSiliconPkg IntelVTdDxe: Remove mVtdHostAddressWidthMask 2018-01-17 10:49:02 +08:00
DmarAcpiTable.c IntelSiliconPkg IntelVTdDxe: Remove mVtdHostAddressWidthMask 2018-01-17 10:49:02 +08:00
IntelVTdDxe.c IntelSiliconPkg IntelVTdDxe: Support early SetAttributes() 2018-01-05 10:26:34 +08:00
IntelVTdDxe.inf IntelSiliconPkg IntelVTdDxe: Use ACPI table event to get DMAR table 2017-11-06 10:08:48 +08:00
IntelVTdDxe.uni
IntelVTdDxeExtra.uni
PciInfo.c
TranslationTable.c IntelSiliconPkg IntelVTdDxe: Fix flush cache issue 2018-01-24 18:40:36 +08:00
TranslationTableEx.c
VtdReg.c IntelSiliconPkg IntelVTdDxe: Remove mVtdHostAddressWidthMask 2018-01-17 10:49:02 +08:00