mirror of https://github.com/acidanthera/audk.git
160 lines
5.4 KiB
C
160 lines
5.4 KiB
C
/** @file
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __OMAP3530PRCM_H__
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#define __OMAP3530PRCM_H__
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#define CM_FCLKEN1_CORE (0x48004A00)
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#define CM_FCLKEN3_CORE (0x48004A08)
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#define CM_ICLKEN1_CORE (0x48004A10)
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#define CM_ICLKEN3_CORE (0x48004A18)
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#define CM_CLKEN2_PLL (0x48004D04)
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#define CM_CLKSEL4_PLL (0x48004D4C)
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#define CM_CLKSEL5_PLL (0x48004D50)
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#define CM_FCLKEN_USBHOST (0x48005400)
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#define CM_ICLKEN_USBHOST (0x48005410)
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#define CM_CLKSTST_USBHOST (0x4800544c)
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//Wakeup clock defintion
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#define CM_FCLKEN_WKUP (0x48004C00)
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#define CM_ICLKEN_WKUP (0x48004C10)
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//Peripheral clock definition
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#define CM_FCLKEN_PER (0x48005000)
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#define CM_ICLKEN_PER (0x48005010)
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#define CM_CLKSEL_PER (0x48005040)
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//Reset management definition
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#define PRM_RSTCTRL (0x48307250)
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#define PRM_RSTST (0x48307258)
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//CORE clock
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#define CM_FCLKEN1_CORE_EN_I2C1_MASK BIT15
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#define CM_FCLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)
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#define CM_FCLKEN1_CORE_EN_I2C1_ENABLE BIT15
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#define CM_ICLKEN1_CORE_EN_I2C1_MASK BIT15
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#define CM_ICLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)
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#define CM_ICLKEN1_CORE_EN_I2C1_ENABLE BIT15
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#define CM_FCLKEN1_CORE_EN_MMC1_MASK BIT24
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#define CM_FCLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)
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#define CM_FCLKEN1_CORE_EN_MMC1_ENABLE BIT24
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#define CM_FCLKEN3_CORE_EN_USBTLL_MASK BIT2
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#define CM_FCLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)
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#define CM_FCLKEN3_CORE_EN_USBTLL_ENABLE BIT2
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#define CM_ICLKEN1_CORE_EN_MMC1_MASK BIT24
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#define CM_ICLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)
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#define CM_ICLKEN1_CORE_EN_MMC1_ENABLE BIT24
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#define CM_ICLKEN3_CORE_EN_USBTLL_MASK BIT2
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#define CM_ICLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)
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#define CM_ICLKEN3_CORE_EN_USBTLL_ENABLE BIT2
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#define CM_CLKEN_FREQSEL_075_100 (0x03UL << 4)
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#define CM_CLKEN_ENABLE (7UL << 0)
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#define CM_CLKSEL_PLL_MULT(x) (((x) & 0x07FF) << 8)
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#define CM_CLKSEL_PLL_DIV(x) ((((x) - 1) & 0x7F) << 0)
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#define CM_CLKSEL_DIV_120M(x) (((x) & 0x1F) << 0)
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#define CM_FCLKEN_USBHOST_EN_USBHOST2_MASK BIT1
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#define CM_FCLKEN_USBHOST_EN_USBHOST2_DISABLE (0UL << 1)
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#define CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE BIT1
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#define CM_FCLKEN_USBHOST_EN_USBHOST1_MASK BIT0
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#define CM_FCLKEN_USBHOST_EN_USBHOST1_DISABLE (0UL << 0)
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#define CM_FCLKEN_USBHOST_EN_USBHOST1_ENABLE BIT0
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#define CM_ICLKEN_USBHOST_EN_USBHOST_MASK BIT0
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#define CM_ICLKEN_USBHOST_EN_USBHOST_DISABLE (0UL << 0)
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#define CM_ICLKEN_USBHOST_EN_USBHOST_ENABLE BIT0
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//Wakeup functional clock
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#define CM_FCLKEN_WKUP_EN_GPIO1_DISABLE (0UL << 3)
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#define CM_FCLKEN_WKUP_EN_GPIO1_ENABLE BIT3
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#define CM_FCLKEN_WKUP_EN_WDT2_DISABLE (0UL << 5)
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#define CM_FCLKEN_WKUP_EN_WDT2_ENABLE BIT5
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//Wakeup interface clock
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#define CM_ICLKEN_WKUP_EN_GPIO1_DISABLE (0UL << 3)
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#define CM_ICLKEN_WKUP_EN_GPIO1_ENABLE BIT3
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#define CM_ICLKEN_WKUP_EN_WDT2_DISABLE (0UL << 5)
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#define CM_ICLKEN_WKUP_EN_WDT2_ENABLE BIT5
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//Peripheral functional clock
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#define CM_FCLKEN_PER_EN_GPT3_DISABLE (0UL << 4)
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#define CM_FCLKEN_PER_EN_GPT3_ENABLE BIT4
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#define CM_FCLKEN_PER_EN_GPT4_DISABLE (0UL << 5)
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#define CM_FCLKEN_PER_EN_GPT4_ENABLE BIT5
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#define CM_FCLKEN_PER_EN_UART3_DISABLE (0UL << 11)
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#define CM_FCLKEN_PER_EN_UART3_ENABLE BIT11
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#define CM_FCLKEN_PER_EN_GPIO2_DISABLE (0UL << 13)
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#define CM_FCLKEN_PER_EN_GPIO2_ENABLE BIT13
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#define CM_FCLKEN_PER_EN_GPIO3_DISABLE (0UL << 14)
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#define CM_FCLKEN_PER_EN_GPIO3_ENABLE BIT14
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#define CM_FCLKEN_PER_EN_GPIO4_DISABLE (0UL << 15)
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#define CM_FCLKEN_PER_EN_GPIO4_ENABLE BIT15
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#define CM_FCLKEN_PER_EN_GPIO5_DISABLE (0UL << 16)
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#define CM_FCLKEN_PER_EN_GPIO5_ENABLE BIT16
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#define CM_FCLKEN_PER_EN_GPIO6_DISABLE (0UL << 17)
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#define CM_FCLKEN_PER_EN_GPIO6_ENABLE BIT17
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//Peripheral interface clock
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#define CM_ICLKEN_PER_EN_GPT3_DISABLE (0UL << 4)
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#define CM_ICLKEN_PER_EN_GPT3_ENABLE BIT4
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#define CM_ICLKEN_PER_EN_GPT4_DISABLE (0UL << 5)
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#define CM_ICLKEN_PER_EN_GPT4_ENABLE BIT5
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#define CM_ICLKEN_PER_EN_UART3_DISABLE (0UL << 11)
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#define CM_ICLKEN_PER_EN_UART3_ENABLE BIT11
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#define CM_ICLKEN_PER_EN_GPIO2_DISABLE (0UL << 13)
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#define CM_ICLKEN_PER_EN_GPIO2_ENABLE BIT13
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#define CM_ICLKEN_PER_EN_GPIO3_DISABLE (0UL << 14)
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#define CM_ICLKEN_PER_EN_GPIO3_ENABLE BIT14
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#define CM_ICLKEN_PER_EN_GPIO4_DISABLE (0UL << 15)
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#define CM_ICLKEN_PER_EN_GPIO4_ENABLE BIT15
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#define CM_ICLKEN_PER_EN_GPIO5_DISABLE (0UL << 16)
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#define CM_ICLKEN_PER_EN_GPIO5_ENABLE BIT16
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#define CM_ICLKEN_PER_EN_GPIO6_DISABLE (0UL << 17)
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#define CM_ICLKEN_PER_EN_GPIO6_ENABLE BIT17
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//Timer source clock selection
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#define CM_CLKSEL_PER_CLKSEL_GPT3_32K (0UL << 1)
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#define CM_CLKSEL_PER_CLKSEL_GPT3_SYS BIT1
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#define CM_CLKSEL_PER_CLKSEL_GPT4_32K (0UL << 2)
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#define CM_CLKSEL_PER_CLKSEL_GPT4_SYS BIT2
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//Reset management (Global and Cold reset)
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#define RST_GS BIT1
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#define RST_DPLL3 BIT2
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#define GLOBAL_SW_RST BIT1
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#define GLOBAL_COLD_RST (0x0UL << 0)
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#endif // __OMAP3530PRCM_H__
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