mirror of https://github.com/acidanthera/audk.git
133 lines
4.0 KiB
C
133 lines
4.0 KiB
C
/**
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Copyright (c) 2009 - 2013, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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/*++
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Module Name:
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PpmPlatformPolicy.h
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Abstract:
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Interface definition details between PPM and platform drivers during DXE phase.
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--*/
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#ifndef _PPM_PLATFORM_POLICY_H_
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#define _PPM_PLATFORM_POLICY_H_
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//
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// PPM policy provided by platform for DXE phase {DDABFEAC-EF63-452c-8F39-ED7FAED8265E}
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//
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#define PPM_PLATFORM_POLICY_PROTOCOL_GUID \
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{0xddabfeac, 0xef63, 0x452c, 0x8f, 0x39, 0xed, 0x7f, 0xae, 0xd8, 0x26, 0x5e}
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//
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// Extern the GUID for protocol users.
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//
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extern EFI_GUID gPpmPlatformPolicyProtocolGuid;
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//
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// Forward reference for ANSI C compatibility
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//
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typedef struct _PPM_PLATFORM_POLICY_PROTOCOL PPM_PLATFORM_POLICY_PROTOCOL;
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//
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// Protocol revision number
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// Any backwards compatible changes to this protocol will result in an update in the revision number
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// Major changes will require publication of a new protocol
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//
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// Revision 1: Original version
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// Revision 2: Added T-states field to the PPM_FUNCTION_ENABLES structure, Renamed unused fields - CxPopUpEnable, CxPopDownEnable, FastC4ExitEnable
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// Revision 3: Extended VidCpuid to 32 bits for extended CPUID support (Penryn)
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// Revision 4: Added support for extended C6 residency enabling
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//
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#define PPM_PLATFORM_POLICY_PROTOCOL_REVISION 1
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#define PPM_PLATFORM_POLICY_PROTOCOL_REVISION_2 2
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#define PPM_PLATFORM_POLICY_PROTOCOL_REVISION_3 3
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#define PPM_PLATFORM_POLICY_PROTOCOL_REVISION_4 4
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//
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// Define maximum number of custom VID states supported
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//
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#ifndef MAX_CUSTOM_VID_TABLE_STATES
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#define MAX_CUSTOM_VID_TABLE_STATES 6
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#endif
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//
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// Custom VID table
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//
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typedef struct {
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UINT8 VidNumber;
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UINT32 VidCpuid;
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UINT16 VidMaxRatio;
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UINT16 VidMaxVid;
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UINT16 StateRatio[MAX_CUSTOM_VID_TABLE_STATES];
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UINT16 StateVid[MAX_CUSTOM_VID_TABLE_STATES];
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} PPM_CUSTOM_VID_TABLE;
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//
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// PPM functional enables
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//
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typedef struct {
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UINT8 EnableGv :1; // 0: Disabled; 1: Enabled
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UINT8 EnableCx :1;
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UINT8 EnableCxe :1;
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UINT8 EnableC4 :1;
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UINT8 EnableC6 :1;
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UINT8 EnableC7 :1;
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UINT8 EnableTm :1;
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UINT8 Reserve00 :1;
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UINT8 Reserve01 :1;
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UINT8 EnableTurboMode :1;
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UINT8 PowerLimit2 :1;
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UINT8 EnableProcHot :1;
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UINT8 Reserve02 :1;
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UINT8 EnableCMP :1;
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UINT8 TStatesEnable :1;
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UINT8 Reserve03 :1;
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UINT8 Reserve04 ;
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} PPM_FUNCTION_ENABLES;
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//
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// PPM Turbo settings
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//
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typedef struct _PPM_TURBO_SETTINGS {
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UINT16 PowerLimit1;
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UINT32 PowerLimit1Time;
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UINT16 PowerLimit2;
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UINT8 TurboPowerLimitLock;
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} PPM_TURBO_SETTINGS;
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//
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// Platform Policy
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//
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struct _PPM_PLATFORM_POLICY_PROTOCOL {
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UINT8 Revision;
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PPM_FUNCTION_ENABLES FunctionEnables;
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PPM_CUSTOM_VID_TABLE CustomVidTable;
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PPM_TURBO_SETTINGS TurboSettings;
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UINT8 Reserve00;
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UINT8 Reserve01;
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UINT8 Reserve02;
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UINT8 Reserve03;
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UINT8 Reserve04;
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UINT8 Reserve05;
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UINT8 Reserve06;
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UINT8 S3RestoreMsrSwSmiNumber;
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UINT8 Reserve07;
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UINT32 Reserve08;
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UINT8 Reserve09;
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//
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// Primary and Secondary Plane Current Limits
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//
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UINT16 Reserve10;
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UINT8 Reserve11;
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};
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#endif
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