mirror of https://github.com/acidanthera/audk.git
76 lines
4.0 KiB
C
76 lines
4.0 KiB
C
/** @file
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*
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* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#ifndef PL35xSMC_H_
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#define PL35xSMC_H_
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#define PL350_SMC_DIRECT_CMD_OFFSET 0x10
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#define PL350_SMC_SET_CYCLES_OFFSET 0x14
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#define PL350_SMC_SET_OPMODE_OFFSET 0x18
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#define PL350_SMC_REFRESH_0_OFFSET 0x20
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#define PL350_SMC_REFRESH_1_OFFSET 0x24
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#define PL350_SMC_DIRECT_CMD_ADDR(addr) ((addr) & 0xFFFFF)
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#define PL350_SMC_DIRECT_CMD_ADDR_SET_CRE (1 << 20)
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#define PL350_SMC_DIRECT_CMD_ADDR_CMD_MODE_UPDATE (3 << 21)
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#define PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE (2 << 21)
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#define PL350_SMC_DIRECT_CMD_ADDR_CMD_MODE (1 << 21)
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#define PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE_AXI (0 << 21)
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#define PL350_SMC_DIRECT_CMD_ADDR_CS_INTERF(interf,chip) (((interf) << 25) | ((chip) << 23))
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#define PL350_SMC_DIRECT_CMD_ADDR_CS(ChipSelect) (((ChipSelect) & 0x7) << 23)
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#define PL350_SMC_SET_OPMODE_MEM_WIDTH_8 (0 << 0)
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#define PL350_SMC_SET_OPMODE_MEM_WIDTH_16 (1 << 0)
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#define PL350_SMC_SET_OPMODE_MEM_WIDTH_32 (2 << 0)
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#define PL350_SMC_SET_OPMODE_SET_RD_SYNC (1 << 2)
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#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_1 (0 << 3)
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#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_4 (1 << 3)
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#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_8 (2 << 3)
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#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_16 (3 << 3)
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#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_32 (4 << 3)
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#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT (5 << 3)
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#define PL350_SMC_SET_OPMODE_SET_WR_SYNC (1 << 6)
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#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_1 (0 << 7)
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#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_4 (1 << 7)
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#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_8 (2 << 7)
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#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_16 (3 << 7)
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#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_32 (4 << 7)
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#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT (5 << 7)
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#define PL350_SMC_SET_OPMODE_SET_BAA (1 << 10)
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#define PL350_SMC_SET_OPMODE_SET_ADV (1 << 11)
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#define PL350_SMC_SET_OPMODE_SET_BLS (1 << 12)
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#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_ANY (0 << 13)
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#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_32 (1 << 13)
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#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_64 (2 << 13)
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#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_128 (3 << 13)
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#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_256 (4 << 13)
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#define PL350_SMC_SET_CYCLE_NAND_T_RC(t) (((t) & 0xF) << 0)
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#define PL350_SMC_SET_CYCLE_NAND_T_WC(t) (((t) & 0xF) << 4)
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#define PL350_SMC_SET_CYCLE_NAND_T_REA(t) (((t) & 0x7) << 8)
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#define PL350_SMC_SET_CYCLE_NAND_T_WP(t) (((t) & 0x7) << 11)
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#define PL350_SMC_SET_CYCLE_NAND_T_CLR(t) (((t) & 0x7) << 14)
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#define PL350_SMC_SET_CYCLE_NAND_T_AR(t) (((t) & 0x7) << 17)
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#define PL350_SMC_SET_CYCLE_NAND_T_RR(t) (((t) & 0x7) << 20)
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#define PL350_SMC_SET_CYCLE_SRAM_T_RC(t) (((t) & 0xF) << 0)
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#define PL350_SMC_SET_CYCLE_SRAM_T_WC(t) (((t) & 0xF) << 4)
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#define PL350_SMC_SET_CYCLE_SRAM_T_CEOE(t) (((t) & 0x7) << 8)
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#define PL350_SMC_SET_CYCLE_SRAM_T_WP(t) (((t) & 0x7) << 11)
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#define PL350_SMC_SET_CYCLE_SRAM_T_PC(t) (((t) & 0x7) << 14)
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#define PL350_SMC_SET_CYCLE_SRAM_T_TR(t) (((t) & 0x7) << 17)
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#define PL350_SMC_SET_CYCLE_SRAM_WE_TIME (1 << 20)
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#endif
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