mirror of https://github.com/acidanthera/audk.git
388 lines
14 KiB
C
388 lines
14 KiB
C
/** @file
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Implementation specific to the SmmCpuFeatureLib library instance
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for AMD based platforms.
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Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
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Copyright (c) Microsoft Corporation.<BR>
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Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Library/SmmCpuFeaturesLib.h>
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#include <Uefi/UefiBaseType.h>
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#include <Register/Amd/SmramSaveStateMap.h>
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#include <Library/BaseLib.h>
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#include <Library/DebugLib.h>
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#include <Library/MmSaveStateLib.h>
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// EFER register LMA bit
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#define LMA BIT10
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// Machine Specific Registers (MSRs)
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#define SMMADDR_ADDRESS 0xC0010112ul
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#define SMMMASK_ADDRESS 0xC0010113ul
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#define EFER_ADDRESS 0XC0000080ul
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// The mode of the CPU at the time an SMI occurs
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STATIC UINT8 mSmmSaveStateRegisterLma;
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/**
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Performs library initialization.
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This initialization function contains common functionality shared betwen all
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library instance constructors.
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**/
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VOID
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CpuFeaturesLibInitialization (
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VOID
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)
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{
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UINT32 LMAValue;
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LMAValue = (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA;
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mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT;
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if (LMAValue) {
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mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;
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}
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}
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/**
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Called during the very first SMI into System Management Mode to initialize
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CPU features, including SMBASE, for the currently executing CPU. Since this
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is the first SMI, the SMRAM Save State Map is at the default address of
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AMD_SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing
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CPU is specified by CpuIndex and CpuIndex can be used to access information
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about the currently executing CPU in the ProcessorInfo array and the
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HotPlugCpuData data structure.
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@param[in] CpuIndex The index of the CPU to initialize. The value
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must be between 0 and the NumberOfCpus field in
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the System Management System Table (SMST).
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@param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that
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was elected as monarch during System Management
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Mode initialization.
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FALSE if the CpuIndex is not the index of the CPU
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that was elected as monarch during System
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Management Mode initialization.
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@param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION
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structures. ProcessorInfo[CpuIndex] contains the
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information for the currently executing CPU.
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@param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure that
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contains the ApidId and SmBase arrays.
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**/
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VOID
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EFIAPI
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SmmCpuFeaturesInitializeProcessor (
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IN UINTN CpuIndex,
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IN BOOLEAN IsMonarch,
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IN EFI_PROCESSOR_INFORMATION *ProcessorInfo,
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IN CPU_HOT_PLUG_DATA *CpuHotPlugData
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)
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{
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AMD_SMRAM_SAVE_STATE_MAP *CpuState;
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UINT32 LMAValue;
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//
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// Configure SMBASE.
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//
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CpuState = (AMD_SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
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CpuState->x64.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
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// Re-initialize the value of mSmmSaveStateRegisterLma flag which might have been changed in PiCpuSmmDxeSmm Driver
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// Entry point, to make sure correct value on AMD platform is assigned to be used by SmmCpuFeaturesLib.
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LMAValue = (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA;
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mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT;
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if (LMAValue) {
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mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;
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}
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//
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// If SMRR is supported, then program SMRR base/mask MSRs.
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// The EFI_MSR_SMRR_PHYS_MASK_VALID bit is not set until the first normal SMI.
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// The code that initializes SMM environment is running in normal mode
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// from SMRAM region. If SMRR is enabled here, then the SMRAM region
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// is protected and the normal mode code execution will fail.
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//
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if (FeaturePcdGet (PcdSmrrEnable)) {
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//
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// SMRR size cannot be less than 4-KBytes
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// SMRR size must be of length 2^n
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// SMRR base alignment cannot be less than SMRR length
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//
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if ((CpuHotPlugData->SmrrSize < SIZE_4KB) ||
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(CpuHotPlugData->SmrrSize != GetPowerOfTwo32 (CpuHotPlugData->SmrrSize)) ||
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((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase))
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{
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//
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// Print message and halt if CPU is Monarch
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//
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if (IsMonarch) {
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DEBUG ((DEBUG_ERROR, "SMM Base/Size does not meet alignment/size requirement!\n"));
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CpuDeadLoop ();
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}
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} else {
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AsmWriteMsr64 (SMMADDR_ADDRESS, CpuHotPlugData->SmrrBase);
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AsmWriteMsr64 (SMMMASK_ADDRESS, ((~(UINT64)(CpuHotPlugData->SmrrSize - 1)) | 0x6600));
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}
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}
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}
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/**
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This function updates the SMRAM save state on the currently executing CPU
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to resume execution at a specific address after an RSM instruction. This
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function must evaluate the SMRAM save state to determine the execution mode
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the RSM instruction resumes and update the resume execution address with
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either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart
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flag in the SMRAM save state must always be cleared. This function returns
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the value of the instruction pointer from the SMRAM save state that was
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replaced. If this function returns 0, then the SMRAM save state was not
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modified.
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This function is called during the very first SMI on each CPU after
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SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode
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to signal that the SMBASE of each CPU has been updated before the default
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SMBASE address is used for the first SMI to the next CPU.
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@param[in] CpuIndex The index of the CPU to hook. The value
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must be between 0 and the NumberOfCpus
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field in the System Management System Table
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(SMST).
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@param[in] CpuState Pointer to SMRAM Save State Map for the
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currently executing CPU.
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@param[in] NewInstructionPointer32 Instruction pointer to use if resuming to
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32-bit execution mode from 64-bit SMM.
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@param[in] NewInstructionPointer Instruction pointer to use if resuming to
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same execution mode as SMM.
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@retval 0 This function did modify the SMRAM save state.
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@retval > 0 The original instruction pointer value from the SMRAM save state
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before it was replaced.
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**/
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UINT64
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EFIAPI
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SmmCpuFeaturesHookReturnFromSmm (
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IN UINTN CpuIndex,
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IN SMRAM_SAVE_STATE_MAP *CpuState,
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IN UINT64 NewInstructionPointer32,
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IN UINT64 NewInstructionPointer
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)
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{
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UINT64 OriginalInstructionPointer;
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AMD_SMRAM_SAVE_STATE_MAP *AmdCpuState;
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AmdCpuState = (AMD_SMRAM_SAVE_STATE_MAP *)CpuState;
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if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
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OriginalInstructionPointer = (UINT64)AmdCpuState->x86._EIP;
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AmdCpuState->x86._EIP = (UINT32)NewInstructionPointer;
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//
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// Clear the auto HALT restart flag so the RSM instruction returns
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// program control to the instruction following the HLT instruction.
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//
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if ((AmdCpuState->x86.AutoHALTRestart & BIT0) != 0) {
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AmdCpuState->x86.AutoHALTRestart &= ~BIT0;
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}
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} else {
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OriginalInstructionPointer = AmdCpuState->x64._RIP;
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if ((AmdCpuState->x64.EFER & LMA) == 0) {
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AmdCpuState->x64._RIP = (UINT32)NewInstructionPointer32;
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} else {
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AmdCpuState->x64._RIP = (UINT32)NewInstructionPointer;
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}
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//
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// Clear the auto HALT restart flag so the RSM instruction returns
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// program control to the instruction following the HLT instruction.
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//
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if ((AmdCpuState->x64.AutoHALTRestart & BIT0) != 0) {
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AmdCpuState->x64.AutoHALTRestart &= ~BIT0;
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}
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}
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return OriginalInstructionPointer;
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}
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/**
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Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is
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returned, then a custom SMI handler is not provided by this library,
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and the default SMI handler must be used.
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@retval 0 Use the default SMI handler.
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@retval > 0 Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler()
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The caller is required to allocate enough SMRAM for each CPU to
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support the size of the custom SMI handler.
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**/
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UINTN
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EFIAPI
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SmmCpuFeaturesGetSmiHandlerSize (
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VOID
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)
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{
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return 0;
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}
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/**
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Install a custom SMI handler for the CPU specified by CpuIndex. This function
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is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater
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than zero and is called by the CPU that was elected as monarch during System
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Management Mode initialization.
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@param[in] CpuIndex The index of the CPU to install the custom SMI handler.
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The value must be between 0 and the NumberOfCpus field
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in the System Management System Table (SMST).
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@param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.
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@param[in] SmiStack The stack to use when an SMI is processed by the
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the CPU specified by CpuIndex.
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@param[in] StackSize The size, in bytes, if the stack used when an SMI is
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processed by the CPU specified by CpuIndex.
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@param[in] GdtBase The base address of the GDT to use when an SMI is
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processed by the CPU specified by CpuIndex.
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@param[in] GdtSize The size, in bytes, of the GDT used when an SMI is
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processed by the CPU specified by CpuIndex.
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@param[in] IdtBase The base address of the IDT to use when an SMI is
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processed by the CPU specified by CpuIndex.
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@param[in] IdtSize The size, in bytes, of the IDT used when an SMI is
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processed by the CPU specified by CpuIndex.
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@param[in] Cr3 The base address of the page tables to use when an SMI
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is processed by the CPU specified by CpuIndex.
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**/
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VOID
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EFIAPI
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SmmCpuFeaturesInstallSmiHandler (
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IN UINTN CpuIndex,
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IN UINT32 SmBase,
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IN VOID *SmiStack,
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IN UINTN StackSize,
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IN UINTN GdtBase,
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IN UINTN GdtSize,
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IN UINTN IdtBase,
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IN UINTN IdtSize,
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IN UINT32 Cr3
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)
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{
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}
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/**
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Determines if MTRR registers must be configured to set SMRAM cache-ability
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when executing in System Management Mode.
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@retval TRUE MTRR registers must be configured to set SMRAM cache-ability.
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@retval FALSE MTRR registers do not need to be configured to set SMRAM
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cache-ability.
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**/
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BOOLEAN
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EFIAPI
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SmmCpuFeaturesNeedConfigureMtrrs (
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VOID
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)
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{
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return FALSE;
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}
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/**
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Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()
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returns TRUE.
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**/
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VOID
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EFIAPI
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SmmCpuFeaturesDisableSmrr (
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VOID
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)
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{
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}
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/**
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Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()
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returns TRUE.
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**/
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VOID
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EFIAPI
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SmmCpuFeaturesReenableSmrr (
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VOID
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)
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{
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}
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/**
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Processor specific hook point each time a CPU enters System Management Mode.
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@param[in] CpuIndex The index of the CPU that has entered SMM. The value
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must be between 0 and the NumberOfCpus field in the
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System Management System Table (SMST).
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**/
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VOID
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EFIAPI
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SmmCpuFeaturesRendezvousEntry (
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IN UINTN CpuIndex
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)
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{
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}
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/**
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Returns the current value of the SMM register for the specified CPU.
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If the SMM register is not supported, then 0 is returned.
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@param[in] CpuIndex The index of the CPU to read the SMM register. The
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value must be between 0 and the NumberOfCpus field in
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the System Management System Table (SMST).
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@param[in] RegName Identifies the SMM register to read.
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@return The value of the SMM register specified by RegName from the CPU
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specified by CpuIndex.
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**/
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UINT64
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EFIAPI
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SmmCpuFeaturesGetSmmRegister (
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IN UINTN CpuIndex,
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IN SMM_REG_NAME RegName
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)
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{
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return 0;
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}
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/**
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Sets the value of an SMM register on a specified CPU.
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If the SMM register is not supported, then no action is performed.
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@param[in] CpuIndex The index of the CPU to write the SMM register. The
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value must be between 0 and the NumberOfCpus field in
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the System Management System Table (SMST).
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@param[in] RegName Identifies the SMM register to write.
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registers are read-only.
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@param[in] Value The value to write to the SMM register.
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**/
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VOID
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EFIAPI
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SmmCpuFeaturesSetSmmRegister (
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IN UINTN CpuIndex,
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IN SMM_REG_NAME RegName,
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IN UINT64 Value
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)
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{
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}
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/**
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Check to see if an SMM register is supported by a specified CPU.
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@param[in] CpuIndex The index of the CPU to check for SMM register support.
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The value must be between 0 and the NumberOfCpus field
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in the System Management System Table (SMST).
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@param[in] RegName Identifies the SMM register to check for support.
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@retval TRUE The SMM register specified by RegName is supported by the CPU
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specified by CpuIndex.
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@retval FALSE The SMM register specified by RegName is not supported by the
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CPU specified by CpuIndex.
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**/
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BOOLEAN
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EFIAPI
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SmmCpuFeaturesIsSmmRegisterSupported (
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IN UINTN CpuIndex,
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IN SMM_REG_NAME RegName
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)
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{
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return FALSE;
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}
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