mirror of https://github.com/acidanthera/audk.git
479 lines
12 KiB
C
479 lines
12 KiB
C
/** @file
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CPU DXE AP Startup
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Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "CpuDxe.h"
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#include "CpuGdt.h"
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#include "CpuMp.h"
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#pragma pack(1)
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typedef struct {
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UINT8 MoveIa32EferMsrToEcx[5];
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UINT8 ReadIa32EferMsr[2];
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UINT8 SetExecuteDisableBitEnableBit[4];
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UINT8 WriteIa32EferMsr[2];
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#if defined (MDE_CPU_IA32)
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UINT8 MovEaxCr3;
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UINT32 Cr3Value;
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UINT8 MovCr3Eax[3];
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UINT8 MoveCr4ToEax[3];
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UINT8 SetCr4Bit5[4];
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UINT8 MoveEaxToCr4[3];
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UINT8 MoveCr0ToEax[3];
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UINT8 SetCr0PagingBit[4];
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UINT8 MoveEaxToCr0[3];
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#endif
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} ENABLE_EXECUTE_DISABLE_CODE;
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ENABLE_EXECUTE_DISABLE_CODE mEnableExecuteDisableCodeTemplate = {
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{ 0xB9, 0x80, 0x00, 0x00, 0xC0 }, // mov ecx, 0xc0000080
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{ 0x0F, 0x32 }, // rdmsr
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{ 0x0F, 0xBA, 0xE8, 0x0B }, // bts eax, 11
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{ 0x0F, 0x30 }, // wrmsr
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#if defined (MDE_CPU_IA32)
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0xB8, 0x00000000, // mov eax, cr3 value
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{ 0x0F, 0x22, 0xd8 }, // mov cr3, eax
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{ 0x0F, 0x20, 0xE0 }, // mov eax, cr4
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{ 0x0F, 0xBA, 0xE8, 0x05 }, // bts eax, 5
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{ 0x0F, 0x22, 0xE0 }, // mov cr4, eax
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{ 0x0F, 0x20, 0xC0 }, // mov eax, cr0
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{ 0x0F, 0xBA, 0xE8, 0x1F }, // bts eax, 31
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{ 0x0F, 0x22, 0xC0 }, // mov cr0, eax
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#endif
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};
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typedef struct {
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UINT8 JmpToCli[2];
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UINT16 GdtLimit;
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UINT32 GdtBase;
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UINT8 Cli;
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UINT8 MovAxRealSegment; UINT16 RealSegment;
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UINT8 MovDsAx[2];
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UINT8 MovBxGdtr[3];
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UINT8 LoadGdt[5];
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UINT8 MovEaxCr0[2];
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UINT32 MovEaxCr0Value;
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UINT8 MovCr0Eax[3];
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UINT8 FarJmp32Flat[2]; UINT32 FlatJmpOffset; UINT16 FlatJmpSelector;
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//
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// Now in IA32
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//
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UINT8 MovEaxCr4;
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UINT32 MovEaxCr4Value;
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UINT8 MovCr4Eax[3];
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UINT8 MoveDataSelectorIntoAx[2]; UINT16 FlatDataSelector;
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UINT8 MoveFlatDataSelectorFromAxToDs[2];
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UINT8 MoveFlatDataSelectorFromAxToEs[2];
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UINT8 MoveFlatDataSelectorFromAxToFs[2];
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UINT8 MoveFlatDataSelectorFromAxToGs[2];
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UINT8 MoveFlatDataSelectorFromAxToSs[2];
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//
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// Code placeholder to enable PAE Execute Disable for IA32
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// and enable Execute Disable Bit for X64
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//
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ENABLE_EXECUTE_DISABLE_CODE EnableExecuteDisable;
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#if defined (MDE_CPU_X64)
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//
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// Transition to X64
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//
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UINT8 MovEaxCr3;
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UINT32 Cr3Value;
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UINT8 MovCr3Eax[3];
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UINT8 MoveCr4ToEax[3];
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UINT8 SetCr4Bit5[4];
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UINT8 MoveEaxToCr4[3];
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UINT8 MoveLongModeEnableMsrToEcx[5];
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UINT8 ReadLmeMsr[2];
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UINT8 SetLongModeEnableBit[4];
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UINT8 WriteLmeMsr[2];
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UINT8 MoveCr0ToEax[3];
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UINT8 SetCr0PagingBit[4];
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UINT8 MoveEaxToCr0[3];
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//UINT8 DeadLoop[2];
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UINT8 FarJmp32LongMode; UINT32 LongJmpOffset; UINT16 LongJmpSelector;
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#endif // defined (MDE_CPU_X64)
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#if defined (MDE_CPU_X64)
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UINT8 MovEaxOrRaxCpuDxeEntry[2]; UINTN CpuDxeEntryValue;
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#else
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UINT8 MovEaxOrRaxCpuDxeEntry; UINTN CpuDxeEntryValue;
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#endif
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UINT8 JmpToCpuDxeEntry[2];
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} STARTUP_CODE;
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#pragma pack()
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/**
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This .asm code used for translating processor from 16 bit real mode into
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64 bit long mode. which help to create the mStartupCodeTemplate value.
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To assemble:
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* nasm -o ApStartup ApStartup.asm
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Then disassemble:
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* ndisasm -b 16 ApStartup
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* ndisasm -b 16 -e 6 ApStartup
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* ndisasm -b 32 -e 32 ApStartup (This -e offset may need adjustment)
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* ndisasm -b 64 -e 0x83 ApStartup (This -e offset may need adjustment)
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%define DEFAULT_CR0 0x00000023
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%define DEFAULT_CR4 0x640
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BITS 16
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jmp short TransitionFromReal16To32BitFlat
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ALIGN 2
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Gdtr:
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dw 0x5a5a
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dd 0x5a5a5a5a
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;
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; Modified: EAX, EBX
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;
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TransitionFromReal16To32BitFlat:
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cli
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mov ax, 0x5a5a
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mov ds, ax
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mov bx, Gdtr
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o32 lgdt [ds:bx]
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mov eax, cr4
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btc eax, 5
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mov cr4, eax
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mov eax, DEFAULT_CR0
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mov cr0, eax
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jmp 0x5a5a:dword jumpTo32BitAndLandHere
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BITS 32
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jumpTo32BitAndLandHere:
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mov eax, DEFAULT_CR4
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mov cr4, eax
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mov ax, 0x5a5a
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mov ds, ax
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mov es, ax
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mov fs, ax
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mov gs, ax
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mov ss, ax
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;
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; Jump to CpuDxe for IA32
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;
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mov eax, 0x5a5a5a5a
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or eax, eax
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jz Transition32FlatTo64Flat
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jmp eax
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;
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; Transition to X64
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;
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Transition32FlatTo64Flat:
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mov eax, 0x5a5a5a5a
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mov cr3, eax
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mov eax, cr4
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bts eax, 5 ; enable PAE
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mov cr4, eax
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mov ecx, 0xc0000080
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rdmsr
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bts eax, 8 ; set LME
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wrmsr
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mov eax, cr0
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bts eax, 31 ; set PG
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mov cr0, eax ; enable paging
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;
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; Jump to CpuDxe for X64
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;
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jmp 0x5a5a:jumpTo64BitAndLandHere
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BITS 64
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jumpTo64BitAndLandHere:
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mov rax, 0xcdcdcdcdcdcdcdcd
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jmp rax
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**/
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STARTUP_CODE mStartupCodeTemplate = {
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{ 0xeb, 0x06 }, // Jump to cli
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0, // GDT Limit
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0, // GDT Base
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0xfa, // cli (Clear Interrupts)
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0xb8, 0x0000, // mov ax, RealSegment
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{ 0x8e, 0xd8 }, // mov ds, ax
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{ 0xBB, 0x02, 0x00 }, // mov bx, Gdtr
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{ 0x3e, 0x66, 0x0f, 0x01, 0x17 }, // lgdt [ds:bx]
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{ 0x66, 0xB8 }, 0x00000023, // mov eax, cr0 value
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{ 0x0F, 0x22, 0xC0 }, // mov cr0, eax
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{ 0x66, 0xEA }, // far jmp to 32-bit flat
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OFFSET_OF(STARTUP_CODE, MovEaxCr4),
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LINEAR_CODE_SEL,
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0xB8, 0x00000640, // mov eax, cr4 value
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{ 0x0F, 0x22, 0xe0 }, // mov cr4, eax
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{ 0x66, 0xb8 }, CPU_DATA_SEL, // mov ax, FlatDataSelector
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{ 0x8e, 0xd8 }, // mov ds, ax
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{ 0x8e, 0xc0 }, // mov es, ax
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{ 0x8e, 0xe0 }, // mov fs, ax
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{ 0x8e, 0xe8 }, // mov gs, ax
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{ 0x8e, 0xd0 }, // mov ss, ax
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#if defined (MDE_CPU_X64)
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//
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// Code placeholder to enable Execute Disable Bit for X64
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// Default is all NOP - No Operation
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//
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{
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{ 0x90, 0x90, 0x90, 0x90, 0x90 },
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{ 0x90, 0x90 },
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{ 0x90, 0x90, 0x90, 0x90 },
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{ 0x90, 0x90 },
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},
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0xB8, 0x00000000, // mov eax, cr3 value
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{ 0x0F, 0x22, 0xd8 }, // mov cr3, eax
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{ 0x0F, 0x20, 0xE0 }, // mov eax, cr4
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{ 0x0F, 0xBA, 0xE8, 0x05 }, // bts eax, 5
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{ 0x0F, 0x22, 0xE0 }, // mov cr4, eax
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{ 0xB9, 0x80, 0x00, 0x00, 0xC0 }, // mov ecx, 0xc0000080
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{ 0x0F, 0x32 }, // rdmsr
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{ 0x0F, 0xBA, 0xE8, 0x08 }, // bts eax, 8
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{ 0x0F, 0x30 }, // wrmsr
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{ 0x0F, 0x20, 0xC0 }, // mov eax, cr0
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{ 0x0F, 0xBA, 0xE8, 0x1F }, // bts eax, 31
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{ 0x0F, 0x22, 0xC0 }, // mov cr0, eax
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0xEA, // FarJmp32LongMode
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OFFSET_OF(STARTUP_CODE, MovEaxOrRaxCpuDxeEntry),
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LINEAR_CODE64_SEL,
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#else
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//
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// Code placeholder to enable PAE Execute Disable for IA32
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// Default is all NOP - No Operation
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//
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{
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{ 0x90, 0x90, 0x90, 0x90, 0x90 },
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{ 0x90, 0x90 },
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{ 0x90, 0x90, 0x90, 0x90 },
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{ 0x90, 0x90 },
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0x90, 0x90909090,
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{ 0x90, 0x90, 0x90 },
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{ 0x90, 0x90, 0x90 },
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{ 0x90, 0x90, 0x90, 0x90 },
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{ 0x90, 0x90, 0x90 },
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{ 0x90, 0x90, 0x90 },
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{ 0x90, 0x90, 0x90, 0x90 },
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{ 0x90, 0x90, 0x90 },
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},
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#endif
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//0xeb, 0xfe, // jmp $
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#if defined (MDE_CPU_X64)
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{ 0x48, 0xb8 }, 0x0, // mov rax, X64 CpuDxe MP Entry Point
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#else
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0xB8, 0x0, // mov eax, IA32 CpuDxe MP Entry Point
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#endif
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{ 0xff, 0xe0 }, // jmp to eax/rax (CpuDxe MP Entry Point)
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};
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volatile STARTUP_CODE *StartupCode = NULL;
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/**
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The function will check if BSP Execute Disable is enabled.
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DxeIpl may have enabled Execute Disable for BSP,
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APs need to get the status and sync up the settings.
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@retval TRUE BSP Execute Disable is enabled.
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@retval FALSE BSP Execute Disable is not enabled.
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**/
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BOOLEAN
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IsBspExecuteDisableEnabled (
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VOID
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)
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{
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UINT32 RegEax;
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UINT32 RegEdx;
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UINT64 MsrRegisters;
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BOOLEAN Enabled;
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Enabled = FALSE;
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AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
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if (RegEax >= 0x80000001) {
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AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);
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//
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// Cpuid 0x80000001
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// Bit 20: Execute Disable Bit available.
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//
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if ((RegEdx & BIT20) != 0) {
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MsrRegisters = AsmReadMsr64 (0xC0000080);
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//
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// Msr 0xC0000080
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// Bit 11: Execute Disable Bit enable.
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//
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if ((MsrRegisters & BIT11) != 0) {
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Enabled = TRUE;
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}
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}
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}
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return Enabled;
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}
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/**
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Prepares Startup Code for APs.
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This function prepares Startup Code for APs.
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@retval EFI_SUCCESS The APs were started
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@retval EFI_OUT_OF_RESOURCES Cannot allocate memory to start APs
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**/
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EFI_STATUS
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PrepareAPStartupCode (
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VOID
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)
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{
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EFI_STATUS Status;
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IA32_DESCRIPTOR Gdtr;
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EFI_PHYSICAL_ADDRESS StartAddress;
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StartAddress = BASE_1MB;
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Status = gBS->AllocatePages (
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AllocateMaxAddress,
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EfiACPIMemoryNVS,
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EFI_SIZE_TO_PAGES (sizeof (*StartupCode)),
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&StartAddress
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);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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StartupCode = (STARTUP_CODE*)(VOID*)(UINTN) StartAddress;
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CopyMem ((VOID*) StartupCode, &mStartupCodeTemplate, sizeof (*StartupCode));
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StartupCode->RealSegment = (UINT16) (((UINTN) StartAddress) >> 4);
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AsmReadGdtr (&Gdtr);
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StartupCode->GdtLimit = Gdtr.Limit;
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StartupCode->GdtBase = (UINT32) Gdtr.Base;
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StartupCode->CpuDxeEntryValue = (UINTN) AsmApEntryPoint;
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StartupCode->FlatJmpOffset += (UINT32) StartAddress;
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if (IsBspExecuteDisableEnabled ()) {
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CopyMem (
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(VOID*) &StartupCode->EnableExecuteDisable,
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&mEnableExecuteDisableCodeTemplate,
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sizeof (ENABLE_EXECUTE_DISABLE_CODE)
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);
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}
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#if defined (MDE_CPU_X64)
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StartupCode->Cr3Value = (UINT32) AsmReadCr3 ();
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StartupCode->LongJmpOffset += (UINT32) StartAddress;
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#else
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StartupCode->EnableExecuteDisable.Cr3Value = (UINT32) AsmReadCr3 ();
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#endif
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return EFI_SUCCESS;
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}
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/**
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Free the code buffer of startup AP.
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**/
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VOID
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FreeApStartupCode (
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VOID
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)
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{
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if (StartupCode != NULL) {
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gBS->FreePages ((EFI_PHYSICAL_ADDRESS)(UINTN)(VOID*) StartupCode,
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EFI_SIZE_TO_PAGES (sizeof (*StartupCode)));
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}
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}
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/**
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Starts the Application Processors and directs them to jump to the
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specified routine.
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The processor jumps to this code in flat mode, but the processor's
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stack is not initialized.
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@retval EFI_SUCCESS The APs were started
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**/
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EFI_STATUS
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StartApsStackless (
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VOID
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)
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{
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SendInitSipiSipiAllExcludingSelf ((UINT32)(UINTN)(VOID*) StartupCode);
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//
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// Wait 100 milliseconds for APs to arrive at the ApEntryPoint routine
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//
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MicroSecondDelay (100 * 1000);
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return EFI_SUCCESS;
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}
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/**
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Resets the Application Processor and directs it to jump to the
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specified routine.
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The processor jumps to this code in flat mode, but the processor's
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stack is not initialized.
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@param ProcessorId the AP of ProcessorId was reset
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**/
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VOID
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ResetApStackless (
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IN UINT32 ProcessorId
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)
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{
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SendInitSipiSipi (ProcessorId,
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(UINT32)(UINTN)(VOID*) StartupCode);
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}
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