mirror of https://github.com/acidanthera/audk.git
f55c76b301
In order to permit the use of compilers that only implement the small code model [which involves the use of ADRP instructions that require 4 KB segment alignment] for generating PE/COFF binaries with a small footprint, we patch ADRP instructions into ADR instructions while doing the ELF to PE/COFF conversion. As it turns out, the linker may be doing the same, but for different reasons: there is a silicon erratum #843419 for ARM Cortex-A53 which affects ADRP instructions appearing at a certain offset in memory, and one of the mitigations for this erratum is to patch them into ADR instructions at link time if the symbol reference is within -/+ 1 MB. However, the LD linker fails to update the static relocation tables, and so we end up with an ADR instruction in the fully linked binary, but with a relocation entry in the RELA section identifying it as an ADRP instruction. Since the linker has already updated the symbol reference, there is no handling needed in GenFw for such instructions, and we can simply treat it as an ordinary ADR. However, since it is guaranteed to be accompanied by an add or load instruction with a LO12 relocation referencing the same symbol, the section offset check we apply to ADR instructions is going to take place anyway, so we can just disregard the ADR instruction entirely. Reported-by: Eugene Cohen <eugene@hp.com> Suggested-by: Eugene Cohen <eugene@hp.com> Tested-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Acked-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> |
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| .. | ||
| BrotliCompress | ||
| Common | ||
| DevicePath | ||
| EfiRom | ||
| GenCrc32 | ||
| GenFfs | ||
| GenFv | ||
| GenFw | ||
| GenSec | ||
| Include | ||
| LzmaCompress | ||
| Makefiles | ||
| PyEfiCompressor | ||
| Split | ||
| TianoCompress | ||
| VfrCompile | ||
| VolInfo | ||
| GNUmakefile | ||
| Makefile | ||