mirror of https://github.com/acidanthera/audk.git
406 lines
13 KiB
Plaintext
406 lines
13 KiB
Plaintext
/** @file
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CPU C State control methods
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Copyright (c) 2013-2015 Intel Corporation.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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DefinitionBlock (
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"Cpu0Cst.aml",
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"SSDT",
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0x01,
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"SsgPmm",
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"Cpu0Cst",
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0x0011
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)
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{
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External(\_PR.CPU0, DeviceObj)
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External (PDC0, IntObj)
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External (CFGD, FieldUnitObj)
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Scope(\_PR.CPU0)
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{
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Method (_CST, 0)
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{
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// If CMP is supported, and OSPM is not capable of independent C1, P, T state
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// support for each processor for multi-processor configuration, we will just report
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// C1 halt
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//
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// PDCx[4] = Indicates whether OSPM is not capable of independent C1, P, T state
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// support for each processor for multi-processor configuration.
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//
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If(LAnd(And(CFGD,0x01000000), LNot(And(PDC0,0x10))))
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{
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Return(Package() {
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1,
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Package()
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{ // C1 halt
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ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
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1,
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157,
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1000
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}
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})
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}
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//
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// If MWAIT extensions is supported and OSPM is capable of performing
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// native C state instructions for the C2/C3 in multi-processor configuration,
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// we report every c state with MWAIT extensions.
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//
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// PDCx[9] = Indicates whether OSPM is capable of performing native C state instructions
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// for the C2/C3 in multi-processor configuration
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//
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If(LAnd(And(CFGD, 0x200000), And(PDC0,0x200)))
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{
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//
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// If C6 is supported, we report MWAIT C1,C2,C4,C6
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//
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If(And(CFGD,0x200))
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{
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Return( Package()
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{
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4,
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Package()
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{ // MWAIT C1, hardware coordinated with no bus master avoidance
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ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},
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1,
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1,
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1000
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},
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Package()
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{ // MWAIT C2, hardware coordinated with no bus master avoidance
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ResourceTemplate(){Register(FFixedHW, 1, 2, 0x10, 1)},
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2,
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20,
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500
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},
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Package()
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{ // MWAIT C4, hardware coordinated with bus master avoidance enabled
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ResourceTemplate(){Register(FFixedHW, 1, 2, 0x30, 3)},
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3,
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100,
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100
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},
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Package()
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{ // MWAIT C6, hardware coordinated with bus master avoidance enabled
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ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 3)},
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3,
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140,
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10
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}
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})
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}
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//
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// If C4 is supported, we report MWAIT C1,C2,C4
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//
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If(And(CFGD,0x080))
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{
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Return( Package()
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{
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3,
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Package()
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{ // MWAIT C1, hardware coordinated with no bus master avoidance
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ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},
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1,
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1,
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1000
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},
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Package()
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{ // MWAIT C2, hardware coordinated with no bus master avoidance
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ResourceTemplate(){Register(FFixedHW, 1, 2, 0x10, 1)},
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2,
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20,
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500
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},
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Package()
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{ // MWAIT C4, hardware coordinated with bus master avoidance enabled
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ResourceTemplate(){Register(FFixedHW, 1, 2, 0x30, 3)},
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3,
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100,
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100
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}
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})
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}
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//
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// If C2 is supported, we report MWAIT C1,C2
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//
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If(And(CFGD,0x020))
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{
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Return( Package()
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{
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2,
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Package()
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{ // MWAIT C1, hardware coordinated with no bus master avoidance
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ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},
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1,
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1,
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1000
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},
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Package()
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{ // MWAIT C2, hardware coordinated with no bus master avoidance
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ResourceTemplate(){Register(FFixedHW, 1, 2, 0x10, 1)},
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2,
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20,
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500
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}
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})
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}
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//
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// Else we only report MWAIT C1.
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//
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Return(Package()
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{
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1,
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Package()
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{ // MWAIT C1, hardware coordinated with no bus master avoidance
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ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},
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1,
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1,
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1000
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}
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})
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}
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// If OSPM is only capable of performing native C state instructions for
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// the C1 in multi-processor configuration, we report C1 with MWAIT, other
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// C states with IO method.
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//
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// PDCx[8] = Indicates whether OSPM is capable of performing native C state instructions
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// for the C1 in multi-processor configuration
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//
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If(LAnd(And(CFGD, 0x200000), And(PDC0,0x100)))
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{
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//
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// If C6 is supported, we report MWAIT C1, IO C2,C4,C6
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//
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If(And(CFGD,0x200))
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{
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Return( Package()
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{
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4,
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Package()
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{ // MWAIT C1, hardware coordinated with no bus master avoidance
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ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},
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1,
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1,
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1000
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},
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Package()
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{ // IO C2 ("PMBALVL2" will be updated at runtime)
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ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},
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2,
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20,
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500
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},
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Package()
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{ // IO C4 ("PMBALVL4" will be updated at runtime)
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ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)},
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3,
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100,
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100
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},
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Package()
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{ // IO C6 ("PMBALVL6" will be updated at runtime)
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ResourceTemplate () {Register(SystemIO, 8, 0, 0x364C564C41424D50)},
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3,
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140,
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10
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}
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})
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}
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//
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// If C4 is supported, we report MWAIT C1, IO C2,C4
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//
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If(And(CFGD,0x080))
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{
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Return( Package()
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{
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3,
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Package()
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{ // MWAIT C1, hardware coordinated with no bus master avoidance
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ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},
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1,
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1,
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1000
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},
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Package()
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{ // IO C2 ("PMBALVL2" will be updated at runtime)
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ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},
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2,
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20,
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500
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},
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Package()
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{ // IO C4 ("PMBALVL4" will be updated at runtime)
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ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)},
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3,
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100,
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100
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}
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})
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}
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//
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// If C2 is supported, we report MWAIT C1, IO C2
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//
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If(And(CFGD,0x020))
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{
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Return( Package()
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{
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2,
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Package()
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{ // MWAIT C1, hardware coordinated with no bus master avoidance
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ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},
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1,
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1,
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1000
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},
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Package()
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{ // IO C2 ("PMBALVL2" will be updated at runtime)
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ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},
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2,
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20,
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500
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}
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})
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}
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//
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// Else we only report MWAIT C1.
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//
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Return(Package()
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{
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1,
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Package()
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{ // MWAIT C1, hardware coordinated with no bus master avoidance
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ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},
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1,
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1,
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1000
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}
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})
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}
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//
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// If MWAIT is not supported, we report all the c states with IO method
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//
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//
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// If C6 is supported, we report C1 halt, IO C2,C4,C6
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//
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If(And(CFGD,0x200))
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{
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Return(Package()
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{
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4,
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Package()
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{ // C1 Halt
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ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},
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1,
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1,
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1000
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},
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Package()
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{ // IO C2 ("PMBALVL2" will be updated at runtime)
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ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},
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2,
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20,
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500
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},
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Package()
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{ // IO C4 ("PMBALVL4" will be updated at runtime)
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ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)},
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3,
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100,
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100
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},
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Package()
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{ // IO C6 ("PMBALVL6" will be updated at runtime)
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ResourceTemplate () {Register(SystemIO, 8, 0, 0x364C564C41424D50)},
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3,
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140,
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10
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}
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})
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}
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//
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// If C4 is supported, we report C1 halt, IO C2,C4
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//
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If(And(CFGD,0x080))
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{
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Return(Package()
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{
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3,
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Package()
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{ // C1 halt
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ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},
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1,
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1,
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1000
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},
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Package()
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{ // IO C2 ("PMBALVL2" will be updated at runtime)
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ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},
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2,
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20,
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500
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},
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Package()
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{ // IO C4 ("PMBALVL4" will be updated at runtime)
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ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)},
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3,
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100,
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100
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}
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})
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}
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//
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// If C2 is supported, we report C1 halt, IO C2
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//
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If(And(CFGD,0x020))
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{
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Return(Package()
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{
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2,
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Package()
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{ // C1 halt
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ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},
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1,
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1,
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1000
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},
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Package()
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{ // IO C2 ("PMBALVL2" will be updated at runtime)
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ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},
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2,
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20,
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500
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}
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})
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}
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//
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// Else we only report C1 halt.
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//
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Return(Package()
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{
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1,
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Package()
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{ // C1 halt
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ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},
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1,
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1,
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1000
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}
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})
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}
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}
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}
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