mirror of https://github.com/acidanthera/audk.git
222 lines
6.4 KiB
NASM
222 lines
6.4 KiB
NASM
;------------------------------------------------------------------------------
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; @file
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; First code executed by processor after resetting.
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; Derived from UefiCpuPkg/ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm
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;
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; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;------------------------------------------------------------------------------
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BITS 16
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ALIGN 16
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;
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; Pad the image size to 4k when page tables are in VTF0
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;
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; If the VTF0 image has page tables built in, then we need to make
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; sure the end of VTF0 is 4k above where the page tables end.
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;
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; This is required so the page tables will be 4k aligned when VTF0 is
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; located just below 0x100000000 (4GB) in the firmware device.
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;
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%ifdef ALIGN_TOP_TO_4K_FOR_PAGING
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TIMES (0x1000 - ($ - EndOfPageTables) - 0x20) DB 0
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%endif
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;
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; Padding to ensure first guid starts at 0xffffffd0
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;
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TIMES (15 - ((guidedStructureEnd - guidedStructureStart + 15) % 16)) DB 0
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; GUIDed structure. To traverse this you should first verify the
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; presence of the table footer guid
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; (96b582de-1fb2-45f7-baea-a366c55a082d) at 0xffffffd0. If that
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; is found, the two bytes at 0xffffffce are the entire table length.
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;
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; The table is composed of structures with the form:
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;
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; Data (arbitrary bytes identified by guid)
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; length from start of data to end of guid (2 bytes)
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; guid (16 bytes)
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;
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; so work back from the footer using the length to traverse until you
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; either find the guid you're looking for or run off the beginning of
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; the table.
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;
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guidedStructureStart:
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%ifdef ARCH_X64
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;
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; TDX Metadata offset block
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;
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; TdxMetadata.asm is included in ARCH_X64 because Inte TDX is only
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; available in ARCH_X64. Below block describes the offset of
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; TdxMetadata block in Ovmf image
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;
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; GUID : e47a6535-984a-4798-865e-4685a7bf8ec2
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;
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tdxMetadataOffsetStart:
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DD fourGigabytes - TdxMetadataGuid - 16
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DW tdxMetadataOffsetEnd - tdxMetadataOffsetStart
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DB 0x35, 0x65, 0x7a, 0xe4, 0x4a, 0x98, 0x98, 0x47
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DB 0x86, 0x5e, 0x46, 0x85, 0xa7, 0xbf, 0x8e, 0xc2
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tdxMetadataOffsetEnd:
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;
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; SEV metadata descriptor
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;
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; Provide the start offset of the metadata blob within the OVMF binary.
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; GUID : dc886566-984a-4798-A75e-5585a7bf67cc
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;
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OvmfSevMetadataOffsetStart:
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DD (fourGigabytes - OvmfSevMetadataGuid)
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DW OvmfSevMetadataOffsetEnd - OvmfSevMetadataOffsetStart
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DB 0x66, 0x65, 0x88, 0xdc, 0x4a, 0x98, 0x98, 0x47
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DB 0xA7, 0x5e, 0x55, 0x85, 0xa7, 0xbf, 0x67, 0xcc
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OvmfSevMetadataOffsetEnd:
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%endif
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; SEV Hash Table Block
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;
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; This describes the guest ram area where the hypervisor should
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; install a table describing the hashes of certain firmware configuration
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; device files that would otherwise be passed in unchecked. The current
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; use is for the kernel, initrd and command line values, but others may be
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; added. The data format is:
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;
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; base physical address (32 bit word)
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; table length (32 bit word)
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;
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; GUID (SEV FW config hash block): 7255371f-3a3b-4b04-927b-1da6efa8d454
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;
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sevFwHashBlockStart:
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DD SEV_FW_HASH_BLOCK_BASE
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DD SEV_FW_HASH_BLOCK_SIZE
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DW sevFwHashBlockEnd - sevFwHashBlockStart
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DB 0x1f, 0x37, 0x55, 0x72, 0x3b, 0x3a, 0x04, 0x4b
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DB 0x92, 0x7b, 0x1d, 0xa6, 0xef, 0xa8, 0xd4, 0x54
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sevFwHashBlockEnd:
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; SEV Secret block
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;
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; This describes the guest ram area where the hypervisor should
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; inject the secret. The data format is:
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;
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; base physical address (32 bit word)
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; table length (32 bit word)
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;
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; GUID (SEV secret block): 4c2eb361-7d9b-4cc3-8081-127c90d3d294
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;
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sevSecretBlockStart:
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DD SEV_LAUNCH_SECRET_BASE
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DD SEV_LAUNCH_SECRET_SIZE
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DW sevSecretBlockEnd - sevSecretBlockStart
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DB 0x61, 0xB3, 0x2E, 0x4C, 0x9B, 0x7D, 0xC3, 0x4C
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DB 0x80, 0x81, 0x12, 0x7C, 0x90, 0xD3, 0xD2, 0x94
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sevSecretBlockEnd:
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;
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; SEV-ES Processor Reset support
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;
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; sevEsResetBlock:
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; For the initial boot of an AP under SEV-ES, the "reset" RIP must be
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; programmed to the RAM area defined by SEV_ES_AP_RESET_IP. The data
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; format is:
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;
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; IP value [0:15]
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; CS segment base [31:16]
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;
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; GUID (SEV-ES reset block): 00f771de-1a7e-4fcb-890e-68c77e2fb44e
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;
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; A hypervisor reads the CS segement base and IP value. The CS segment base
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; value represents the high order 16-bits of the CS segment base, so the
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; hypervisor must left shift the value of the CS segement base by 16 bits to
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; form the full CS segment base for the CS segment register. It would then
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; program the EIP register with the IP value as read.
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;
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sevEsResetBlockStart:
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DD SEV_ES_AP_RESET_IP
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DW sevEsResetBlockEnd - sevEsResetBlockStart
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DB 0xDE, 0x71, 0xF7, 0x00, 0x7E, 0x1A, 0xCB, 0x4F
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DB 0x89, 0x0E, 0x68, 0xC7, 0x7E, 0x2F, 0xB4, 0x4E
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sevEsResetBlockEnd:
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;
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; Table footer:
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;
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; length of whole table (16 bit word)
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; GUID (table footer): 96b582de-1fb2-45f7-baea-a366c55a082d
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;
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DW guidedStructureEnd - guidedStructureStart
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DB 0xDE, 0x82, 0xB5, 0x96, 0xB2, 0x1F, 0xF7, 0x45
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DB 0xBA, 0xEA, 0xA3, 0x66, 0xC5, 0x5A, 0x08, 0x2D
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guidedStructureEnd:
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ALIGN 16
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applicationProcessorEntryPoint:
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;
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; Application Processors entry point
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;
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; GenFv generates code aligned on a 4k boundary which will jump to this
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; location. (0xffffffe0) This allows the Local APIC Startup IPI to be
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; used to wake up the application processors.
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;
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jmp EarlyApInitReal16
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ALIGN 8
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DD 0
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;
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; The VTF signature
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;
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; VTF-0 means that the VTF (Volume Top File) code does not require
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; any fixups.
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;
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vtfSignature:
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DB 'V', 'T', 'F', 0
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ALIGN 16
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resetVector:
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;
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; Reset Vector
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;
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; This is where the processor will begin execution
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;
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; In IA32 we follow the standard reset vector flow. While in X64, Td guest
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; may be supported. Td guest requires the startup mode to be 32-bit
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; protected mode but the legacy VM startup mode is 16-bit real mode.
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; To make NASM generate such shared entry code that behaves correctly in
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; both 16-bit and 32-bit mode, more BITS directives are added.
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;
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%ifdef ARCH_IA32
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nop
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nop
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jmp EarlyBspInitReal16
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%else
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mov eax, cr0
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test al, 1
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jz .Real
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BITS 32
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jmp Main32
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BITS 16
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.Real:
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jmp EarlyBspInitReal16
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%endif
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ALIGN 16
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fourGigabytes:
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