mirror of https://github.com/acidanthera/audk.git
283 lines
12 KiB
C
283 lines
12 KiB
C
/** @file
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* File managing the MMU for ARMv7 architecture
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <Uefi.h>
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#include <Chipset/ArmV7.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/ArmLib.h>
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#include <Library/BaseLib.h>
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#include <Library/DebugLib.h>
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#include "ArmV7Lib.h"
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#include "ArmLibPrivate.h"
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VOID
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PopulateLevel2PageTable (
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IN UINT32 *SectionEntry,
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IN UINT32 PhysicalBase,
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IN UINT32 RemainLength,
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IN ARM_MEMORY_REGION_ATTRIBUTES Attributes
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) {
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UINT32* PageEntry;
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UINT32 Pages;
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UINT32 Index;
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UINT32 PageAttributes;
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UINT32 SectionDescriptor;
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UINT32 TranslationTable;
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UINT32 BaseSectionAddress;
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switch (Attributes) {
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case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
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case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK:
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PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK;
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
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case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH:
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PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_THROUGH;
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
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case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE:
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PageAttributes = TT_DESCRIPTOR_PAGE_DEVICE;
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
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case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED:
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PageAttributes = TT_DESCRIPTOR_PAGE_UNCACHED;
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break;
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default:
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PageAttributes = TT_DESCRIPTOR_PAGE_UNCACHED;
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break;
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}
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// Check if the Section Entry has already been populated. Otherwise attach a
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// Level 2 Translation Table to it
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if (*SectionEntry != 0) {
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// The entry must be a page table. Otherwise it exists an overlapping in the memory map
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if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(*SectionEntry)) {
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TranslationTable = *SectionEntry & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK;
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} else if ((*SectionEntry & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) {
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// Case where a virtual memory map descriptor overlapped a section entry
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// Allocate a Level2 Page Table for this Section
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TranslationTable = (UINTN)AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_PAGE_SIZE + TRANSLATION_TABLE_PAGE_ALIGNMENT));
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TranslationTable = ((UINTN)TranslationTable + TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK;
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// Translate the Section Descriptor into Page Descriptor
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SectionDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE;
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SectionDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(*SectionEntry,0);
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SectionDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(*SectionEntry);
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SectionDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(*SectionEntry,0);
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SectionDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(*SectionEntry);
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SectionDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_S(*SectionEntry);
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BaseSectionAddress = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(*SectionEntry);
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// Populate the new Level2 Page Table for the section
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PageEntry = (UINT32*)TranslationTable;
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for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) {
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PageEntry[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseSectionAddress + (Index << 12)) | SectionDescriptor;
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}
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// Overwrite the section entry to point to the new Level2 Translation Table
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*SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) |
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(IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(Attributes) ? (1 << 3) : 0) |
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TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;
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} else {
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// We do not support the other section type (16MB Section)
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ASSERT(0);
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return;
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}
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} else {
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TranslationTable = (UINTN)AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_PAGE_SIZE + TRANSLATION_TABLE_PAGE_ALIGNMENT));
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TranslationTable = ((UINTN)TranslationTable + TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK;
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ZeroMem ((VOID *)TranslationTable, TRANSLATION_TABLE_PAGE_SIZE);
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*SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) |
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(IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(Attributes) ? (1 << 3) : 0) |
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TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;
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}
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PageEntry = ((UINT32 *)(TranslationTable) + ((PhysicalBase & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT));
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Pages = RemainLength / TT_DESCRIPTOR_PAGE_SIZE;
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for (Index = 0; Index < Pages; Index++) {
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*PageEntry++ = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(PhysicalBase) | PageAttributes;
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PhysicalBase += TT_DESCRIPTOR_PAGE_SIZE;
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}
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}
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VOID
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FillTranslationTable (
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IN UINT32 *TranslationTable,
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IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
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)
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{
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UINT32 *SectionEntry;
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UINT32 Attributes;
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UINT32 PhysicalBase = MemoryRegion->PhysicalBase;
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UINT32 RemainLength = MemoryRegion->Length;
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ASSERT(MemoryRegion->Length > 0);
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switch (MemoryRegion->Attributes) {
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case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
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Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
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Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
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Attributes = TT_DESCRIPTOR_SECTION_DEVICE(0);
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
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Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK:
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Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH:
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Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE:
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Attributes = TT_DESCRIPTOR_SECTION_DEVICE(1);
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED:
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Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1);
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break;
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default:
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Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
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break;
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}
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// Get the first section entry for this mapping
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SectionEntry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
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while (RemainLength != 0) {
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if (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE == 0) {
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if (RemainLength >= TT_DESCRIPTOR_SECTION_SIZE) {
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// Case: Physical address aligned on the Section Size (1MB) && the length is greater than the Section Size
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*SectionEntry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
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PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
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} else {
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// Case: Physical address aligned on the Section Size (1MB) && the length does not fill a section
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PopulateLevel2PageTable(SectionEntry++,PhysicalBase,RemainLength,MemoryRegion->Attributes);
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// It must be the last entry
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break;
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}
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} else {
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// Case: Physical address NOT aligned on the Section Size (1MB)
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PopulateLevel2PageTable(SectionEntry++,PhysicalBase,RemainLength,MemoryRegion->Attributes);
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// Aligned the address
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PhysicalBase = (PhysicalBase + TT_DESCRIPTOR_SECTION_SIZE) & ~(TT_DESCRIPTOR_SECTION_SIZE-1);
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// If it is the last entry
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if (RemainLength < TT_DESCRIPTOR_SECTION_SIZE) {
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break;
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}
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}
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RemainLength -= TT_DESCRIPTOR_SECTION_SIZE;
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}
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}
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VOID
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EFIAPI
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ArmConfigureMmu (
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IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
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OUT VOID **TranslationTableBase OPTIONAL,
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OUT UINTN *TranslationTableSize OPTIONAL
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)
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{
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UINTN TranslationTable;
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ARM_MEMORY_REGION_ATTRIBUTES TranslationTableAttribute;
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UINT32 TTBRAttributes;
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// Allocate pages for translation table.
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TranslationTable = (UINTN)AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SECTION_SIZE + TRANSLATION_TABLE_SECTION_ALIGNMENT));
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TranslationTable = ((UINTN)TranslationTable + TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK;
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if (TranslationTableBase != NULL) {
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*TranslationTableBase = (VOID *)TranslationTable;
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}
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if (TranslationTableBase != NULL) {
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*TranslationTableSize = TRANSLATION_TABLE_SECTION_SIZE;
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}
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ZeroMem ((VOID *)TranslationTable, TRANSLATION_TABLE_SECTION_SIZE);
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ArmCleanInvalidateDataCache();
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ArmInvalidateInstructionCache();
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ArmInvalidateTlb();
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ArmDisableDataCache();
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ArmDisableInstructionCache();
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ArmDisableMmu();
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// Make sure nothing sneaked into the cache
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ArmCleanInvalidateDataCache();
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ArmInvalidateInstructionCache();
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TranslationTableAttribute = (ARM_MEMORY_REGION_ATTRIBUTES)0;
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while (MemoryTable->Length != 0) {
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// Find the memory attribute for the Translation Table
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if ((TranslationTable >= MemoryTable->PhysicalBase) && (TranslationTable < MemoryTable->PhysicalBase + MemoryTable->Length)) {
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TranslationTableAttribute = MemoryTable->Attributes;
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}
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FillTranslationTable ((VOID *)TranslationTable, MemoryTable);
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MemoryTable++;
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}
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// Translate the Memory Attributes into Translation Table Register Attributes
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if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) ||
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(TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED)) {
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TTBRAttributes = TTBR_NON_CACHEABLE;
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} else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||
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(TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK)) {
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TTBRAttributes = TTBR_WRITE_BACK_ALLOC;
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} else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) ||
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(TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH)) {
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TTBRAttributes = TTBR_WRITE_THROUGH_NO_ALLOC;
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} else {
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//TODO: We should raise an error here
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TTBRAttributes = TTBR_NON_CACHEABLE;
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}
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ArmSetTTBR0 ((VOID *)(UINTN)((TranslationTable & 0xFFFFC000) | (TTBRAttributes & 0x7F)));
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ArmSetDomainAccessControl (DOMAIN_ACCESS_CONTROL_NONE(15) |
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DOMAIN_ACCESS_CONTROL_NONE(14) |
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DOMAIN_ACCESS_CONTROL_NONE(13) |
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DOMAIN_ACCESS_CONTROL_NONE(12) |
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DOMAIN_ACCESS_CONTROL_NONE(11) |
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DOMAIN_ACCESS_CONTROL_NONE(10) |
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DOMAIN_ACCESS_CONTROL_NONE( 9) |
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DOMAIN_ACCESS_CONTROL_NONE( 8) |
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DOMAIN_ACCESS_CONTROL_NONE( 7) |
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DOMAIN_ACCESS_CONTROL_NONE( 6) |
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DOMAIN_ACCESS_CONTROL_NONE( 5) |
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DOMAIN_ACCESS_CONTROL_NONE( 4) |
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DOMAIN_ACCESS_CONTROL_NONE( 3) |
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DOMAIN_ACCESS_CONTROL_NONE( 2) |
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DOMAIN_ACCESS_CONTROL_NONE( 1) |
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DOMAIN_ACCESS_CONTROL_MANAGER(0));
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ArmEnableInstructionCache();
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ArmEnableDataCache();
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ArmEnableMmu();
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}
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